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MC68HC908JL3E MC68HC908JK3E MC68HC908JK1E MC68HRC908JL3E MC68HRC908JK3E MC68HRC908JK1E MC68HLC908JL3E MC68HLC908JK3E MC68HLC908JK1E
M68HC08
Microcontrollers
Technical Data
MC68HC908JL3E/D Rev. 2, 12/2002
MOTOROLA.COM/SEMICONDUCTORS
MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E
Technical Data
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and the Stylized M logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2002
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data 3
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision Level Description Added appendix A for low-volt devices. Dec 2002 2 Updated Monitor Mode Circuit (Figure 9-1) and Monitor Mode Entry Requirements and Options (Table 9-1) in Monitor ROM section. First general release. Page Number(s) 217-224 109, 110 --
May 2002
1
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MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 41 Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 43 Section 5. Configuration Register (CONFIG) . . . . . . . . . 53 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 57 Section 7. System Integration Module (SIM) . . . . . . . . . 77 Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . 101 Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . 107 Section 10. Timer Interface Module (TIM) . . . . . . . . . . . 121 Section 11. Analog-to-Digital Converter (ADC) . . . . . . 143 Section 12. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 153 Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . . 165 Section 14. Keyboard Interrupt Module (KBI). . . . . . . . 171 Section 15. Computer Operating Properly (COP) . . . . 179 Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 185 Section 17. Break Module (BREAK) . . . . . . . . . . . . . . . 189 Section 18. Electrical Specifications. . . . . . . . . . . . . . . 197 Section 19. Mechanical Specifications . . . . . . . . . . . . . 209 Section 20. Ordering Information . . . . . . . . . . . . . . . . . 213 Appendix A. MC68HLC908JL3E/JK3E/JK1E. . . . . . . . . 217
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List of Sections
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Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 1.5 1.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 2. Memory Map
2.1 2.2 2.3 2.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Section 3. Random-Access Memory (RAM)
3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 4. FLASH Memory (FLASH)
4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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4.4 4.5 4.6 4.7 4.8 4.9 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 46 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 50
Section 5. Configuration Register (CONFIG)
5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Section 6. Central Processor Unit (CPU)
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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Section 7. System Integration Module (SIM)
7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 81 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 81 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 83 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 85 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 86 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 86 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .87 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 94 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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7.8.1 7.8.2 7.8.3 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . 97 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . 98 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 100
Section 8. Oscillator (OSC)
8.1 8.2 8.3 8.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E). . . . . . . . . . . 102 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . 103
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 104 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . 104 8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 104 8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . 104 8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . 105 8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 106
Section 9. Monitor ROM (MON)
9.1 9.2 9.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
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9.4.6 9.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Section 10. Timer Interface Module (TIM)
10.1 10.2 10.3 10.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 126 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 127 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 127 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 128 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 129 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.8 10.9 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .134 10.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 136 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 137 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) .138 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 142
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Table of Contents
Section 11. Analog-to-Digital Converter (ADC)
11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 148 11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 151
Section 12. Input/Output (I/O) Ports
12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 157 12.3.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . 158 12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 160
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12.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 162 12.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 163 12.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 164
Section 13. External Interrupt (IRQ)
13.1 13.2 13.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.5 13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .169 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 169
Section 14. Keyboard Interrupt Module (KBI)
14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 175 14.4.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 176 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.6 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .177
Section 15. Computer Operating Properly (COP)
15.1 15.2 15.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5 15.6 15.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .184
Section 16. Low Voltage Inhibit (LVI)
16.1 16.2 16.3 16.4 16.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 186
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Section 17. Break Module (BREAK)
17.1 17.2 17.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .192 17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 193 17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .194 17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 196 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Section 18. Electrical Specifications
18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 199 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 200 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 202 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 203
18.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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Section 19. Mechanical Specifications
19.1 19.2 19.3 19.4 19.5 19.6 19.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Section 20. Ordering Information
20.1 20.2 20.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Appendix A. MC68HLC908JL3E/JK3E/JK1E
A.1 A.2 A.3 A.4 A.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Oscillator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
A.6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 A.6.1 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . 218 A.6.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 219 A.6.3 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 A.6.4 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .220 A.6.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 A.6.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 A.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
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Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 Title Page
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 28-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 27 20-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 27 48-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 34 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 44 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 45 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 49 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 50 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .54 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .55 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 62 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Figure 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 Title Page
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .92 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .92 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .93 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . . 95 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . . 95 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . . 97 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .100 X-tal Oscillator External Connections . . . . . . . . . . . . . . . . . . . 102 RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . 103 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 112 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 128 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 134 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 136 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 137 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 138 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 142
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Figure 11-1 11-2 11-3 11-4 11-5 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4
Title
Page
ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .144 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 148 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .151 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .156 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 157 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . 158 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .159 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 160 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .162 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 163 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . 164 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .167 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 169 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .170 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . 172 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 175 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 176
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .182 15-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .183 16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .186 16-3 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .187
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Technical Data 19
List of Figures
Figure 17-1 17-2 17-3 17-4 17-5 17-6 17-7 18-1 18-2 18-3 18-4 18-5 18-6 Title Page
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 191 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 191 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 193 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 194 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 194 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 194 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .196 RC vs. Frequency (5V @25C) . . . . . . . . . . . . . . . . . . . . . . . 202 RC vs. Frequency (3V @25C) . . . . . . . . . . . . . . . . . . . . . . . 205 Typical Operating IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned On (25 C) . . . . . . . . . . . . . . . . . 206 Typical Operating IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned On (25 C) . . . . . . . . . . . . . . . . . 206 Typical Wait Mode IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 C) . . . . . . . . . . . . . . . . . 207 Typical Wait Mode IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 C) . . . . . . . . . . . . . . . . . 207 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .212 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . . 213 48-Pin LQFP (Case #932) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19-1 19-2 19-3 19-4 19-5
Technical Data 20 List of Figures
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
List of Tables
Table 1-1 1-2 2-1 6-1 6-2 7-1 7-2 7-3 7-4 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Title Page
Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Monitor Mode Entry Requirements and Options. . . . . . . . . . . 110 Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . .113 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 113 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 116 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 116 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 117 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 117 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .118 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 118
10-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .140 11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA List of Tables
Technical Data 21
List of Tables
Table 12-1 12-2 12-3 12-4 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 Title Page
Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 155 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DC Electrical Characteristics (5V) . . . . . . . . . . . . . . . . . . . . . 200 Control Timing (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Oscillator Component Specifications (5V) . . . . . . . . . . . . . . . 202 DC Electrical Characteristics (3V) . . . . . . . . . . . . . . . . . . . . . 203 Control Timing (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Oscillator Component Specifications (3V) . . . . . . . . . . . . . . . 205 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 A-1 A-2 A-3 A-4 A-5 A-6 A-7 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 219 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Oscillator Component Specifications . . . . . . . . . . . . . . . . . . .220 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 MC68HLC908JL3E/JK3E/JK1E Order Numbers . . . . . . . . . . 223
Technical Data 22 List of Tables
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2 Introduction
The MC68H(R)C908JL3E is a member of the low-cost, highperformance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Table 1-1. Summary of Device Variations
Device MC68HC908JL3E MC68HRC908JL3E MC68HC908JK3E MC68HRC908JK3E MC68HC908JK1E MC68HRC908JK1E Oscillator Option X-TAL 4096 bytes RC X-TAL 4096 bytes RC X-TAL 1536 bytes RC 20 20 28 FLASH Memory Size Pin Count
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA General Description
Technical Data 23
General Description
All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E and MC68H(R)C908JK1E, unless otherwise stated.
1.3 Features
Features of the MC68H(R)C908JL3E include the following: * * * * * EMC enhanced version of MC68H(R)C908JL3/JK3/JK1 High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families Low-power design; fully static with stop and wait modes Maximum internal bus frequency: - 8-MHz at 5V operating voltage - 4-MHz at 3V operating voltage * Oscillator options: - Crystal oscillator for MC68HC908JL3E/JK3E/JK1E - RC oscillator for MC68HRC908JL3E/JK3E/JK1E * User program FLASH memory with security1 feature - 4,096 bytes for MC68H(R)C908JL3E/JK3E - 1,536 bytes for MC68H(R)C908JK1E * * * * 128 bytes of on-chip RAM 2-channel, 16-bit timer interface module (TIM) 12-channel, 8-bit analog-to-digital converter (ADC) 23 general purpose I/O ports for MC68H(R)C908JL3E: - 7 keyboard interrupt with internal pull-up (6 keyboard interrupt for MC68HC908JL3E) - 10 LED drivers (sink) - 2 x 25mA open-drain I/O with pull-up
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Technical Data 24 General Description
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
General Description Features
*
15 general purpose I/O ports for MC68H(R)C908JK3E/JK1E: - 1 keyboard interrupt with internal pull-up (MC68HRC908JK3E/JK1E only) - 4 LED drivers (sink) - 2 x 25mA open-drain I/O with pull-up - 10-channel ADC
*
System protection features: - Optional computer operating properly (COP) reset - Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation - Illegal opcode detection with reset - Illegal address detection with reset
* * * *
Master reset pin with internal pull-up and power-on reset IRQ1 with schmitt-trigger input and programmable pull-up 28-pin PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H(R)C908JL3E 20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3E/JK1E
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support
Technical Data General Description 25
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
General Description 1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68H(R)C908JL3E.
INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU)
KEYBOARD INTERRUPT MODULE PORTA DDRA
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH: MC68H(R)C908JK3E/JL3E -- 4,096 BYTES MC68H(R)C908JK1E -- 1,536 BYTES USER RAM -- 128 BYTES MONITOR ROM -- 960 BYTES USER FLASH VECTOR SPACE -- 48 BYTES
MC68HC908JL3E/JK3E/JK1E
8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE
PTA6/KBI6** PTA5/KBI5** PTA4/KBI4** PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 PTD7** PTD6** PTD5/TCH1 PTD4/TCH0 PTD3/ADC8 PTD2/ADC9 PTD1/ADC10 PTD0/ADC11
#
2-CHANNEL TIMER INTERFACE MODULE PORTB PORTD
BREAK MODULE
OSC1
X-TAL OSCILLATOR OSC2
MC68HRC908JL3E/JK3E/JK1E
COMPUTER OPERATING PROPERLY MODULE
RC OSCILLATOR DDRD POWER-ON RESET MODULE * RST SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE * IRQ1 EXTERNAL INTERRUPT MODULE * Pin contains integrated pull-up device. ** Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. # Pins available on MC68H(R)C908JL3E only. Shared pin: MC68HC908JL3E/JK3E/JK1E -- OSC2 MC68HRC908JL3E/JK3E/JK1E -- RCCLK/PTA6/KBI6
DDRB
#
VDD POWER VSS ADC REFERENCE
Figure 1-1. MCU Block Diagram
Technical Data 26 General Description
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
General Description Pin Assignments
1.5 Pin Assignments
IRQ1 PTA0/KBI0 VSS OSC1 OSC2/RCCLK/PTA6/KBI PTA1/KBI1 VDD PTA2/KBI2 PTA3/KBI3 PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTD7 PTD6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RST PTA5/KBI5 PTD4/TCH0 PTD5/TCH1 PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 PTB2/ADC2 PTB3/ADC3 PTD0/ADC11 PTB4/ADC4
MC68H(R)C908JL3E Figure 1-2. 28-Pin PDIP/SOIC Pin Assignment
IRQ1 VSS OSC1 OSC2/RCCLK/PTA6/KBI VDD PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTD7 PTD6
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RST PTD4/TCH0 PTD5/TCH1 PTD2/ADC9 PTD3/ADC8 PTB0/ADC0 PTB1/ADC1 PTB2/ADC2 PTB3/ADC3 PTB4/ADC4
Pins not available on 20-pin packages PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 Internal pads are unconnected. PTD0/ADC11 PTD1/ADC10
MC68H(R)C908JK3E/JK1E Figure 1-3. 20-Pin PDIP/SOIC Pin Assignment
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA General Description
Technical Data 27
General Description
PTD4/TCH0
PTD5/TCH1
PTA0/KBI0
PTA5/KBI5
IRQ1
VSS
RST
NC
NC
NC 38
47
46
45
44
43
42
41
40
39
37 NC 36 NC
NC 1 NC OSC1 OSC2/RCCLK/PTA6/KBI6 PTA1/KBI1 NC VDD PTA2/KBI2 PTA3KBI3 PTB7/ADC7 NC NC 12 NC 13 2 3 4 5 6 7 8 9 10 11 20 21 22 14 15 16 17 18 19 23 35 34 33 32
48 NC
NC NC PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 NC PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 NC
25 NC
MC68H(R)C908JL3E
31 30 29 28 27 26
PTD7
PTB6/ADC6
PTB5/ADC5
PTD6
PTB4/ADC4
PTB3/ADC3
NC: No connection
Figure 1-4. 48-Pin LQFP Pin Assignment
Technical Data 28 General Description
PTD0/ADC11
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
PTB2/ADC2
NC 24
NC
NC
General Description Pin Functions
1.6 Pin Functions
Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions
PIN NAME VDD VSS RST Power supply. Power supply ground RESET input, active low. With Internal pull-up and schmitt trigger input. External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection. X-tal or RC oscillator input. MC68HC908JL3E/JK3E/JK1E: X-tal oscillator output, this is the inverting OSC1 signal. OSC2 MC68HRC908JL3E/JK3E/JK1E: Default is RC oscillator clock output, RCCLK. Shared with PTA6/KBI6, with programmable pull-up. 7-bit general purpose I/O port. Shared with 7 keyboard interrupts KBI[0:6]. PTA[0:6] Each pin has programmable internal pull-up device. PTA[0:5] have LED direct sink capability 8-bit general purpose I/O port. PTB[0:7] Shared with 8 ADC inputs, ADC[0:7]. 8-bit general purpose I/O port. PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. PTD[0:7] PTD[4:5] shared with TIM channels, TCH0 and TCH1. PTD[2:3], PTD[6:7] have LED direct sink capability PTD[6:7] can be configured as 25mA open-drain output with pull-up. In In/Out Input In/Out In In/Out Analog VDD Analog VDD VSS VDD In In In/Out VDD VSS VDD In/Out In/Out In VDD VDD VDD PIN DESCRIPTION IN/OUT In Out Input VOLTAGE LEVEL 5V or 3V 0V VDD
IRQ1
Input
VDD to VDD+VHI
OSC1
In Out
Analog Analog
NOTE:
On the MC68H(R)C908JK3E/JK1E, the following pins are not available: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.
Technical Data General Description 29
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
General Description
Technical Data 30 General Description
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 2. Memory Map
2.1 Contents
2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * 4,096 bytes of user FLASH -- MC68H(R)C908JL3E/JK3E 1,536 bytes of user FLASH -- MC68H(R)C908JK1E 128 bytes of RAM 48 bytes of user-defined vectors 960 bytes of Monitor ROM
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 31
Memory Map
$0000 $003F $0040 $007F $0080 $00FF $0100 $EBFF $EC00 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF
I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 60,160 BYTES
UNIMPLEMENTED 62,720 BYTES
$0100 $F5FF $F600 $FBFF
FLASH MEMORY MC68H(R)C908JL3E/JK3E 4,096 BYTES
FLASH MEMORY MC68H(R)C908JK1E 1,536 BYTES
MONITOR ROM 512 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (RSR) RESERVED (UBAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) FLASH BLOCK PROTECT REGISTER (FLBPR) RESERVED RESERVED BREAK ADDRESS HIGH REGISTER (BRKH) BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) RESERVED MONITOR ROM 448 BYTES USER VECTORS 48 BYTES
Figure 2-1. Memory Map
Technical Data 32 Memory Map MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Memory Map I/O Section
2.3 I/O Section
Addresses $0000-$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: * * * * * * * * * * * * * * * * * $FE00; Break Status Register, BSR $FE01; Reset Status Register, RSR $FE02; Reserved $FE03; Break Flag Control Register, BFCR $FE04; Interrupt Status Register 1, INT1 $FE05; Interrupt Status Register 2, INT2 $FE06; Interrupt Status Register 3, INT3 $FE07; Reserved $FE08; FLASH Control Register, FLCR $FE09; FLASH Block Protect Register, FLBPR $FE0A; Reserved $FE0B; Reserved $FE0C; Break Address Register High, BRKH $FE0D; Break Address Register Low, BRKL $FE0E; Break Status and Control Register, BRKSCR $FE0F; Reserved $FFFF; COP Control Register, COPCTL
2.4 Monitor ROM
The 960 bytes at addresses $FC00-$FDFF and $FE10-$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Section 9. Monitor ROM (MON).)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 33
Memory Map
Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read:
Bit 7 0
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset
$0002
Unimplemented Write:
$0003
Read: Port D Data Register Write: (PTD) Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset 0 DDRA6 0 DDRB6 0 DDRA5 0 DDRB5 0 DDRA4 0 DDRB4 0 DDRA3 0 DDRB3 0 DDRA2 0 DDRB2 0 DDRA1 0 DDRB1 0 DDRA0 0 DDRB0 0
Read: Data Direction Register A $0004 Write: (DDRA) Reset:
0
Read: DDRB7 Data Direction Register B $0005 Write: (DDRB) Reset: 0 Read: $0006 Unimplemented Write:
Read: DDRD7 Data Direction Register D $0007 Write: (DDRD) Reset: 0 $0008 $0009 Read: Unimplemented Write:
DDRD6 0
DDRD5 0
DDRD4 0
DDRD3 0
DDRD2 0
DDRD1 0
DDRD0 0
$000A
Read: Port D Control Register Write: (PDCR) Reset:
0
0
0
0
SLOWD7 SLOWD6 PTDPU7 0 R 0 = Reserved 0
PTDPU6 0
0
0
0
0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
Technical Data 34 Memory Map
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr. $000B $000C
Register Name Read: Unimplemented Write:
Bit 7
6
5
4
3
2
1
Bit 0
$000D
Read: Port A Input Pull-up PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Enable Register Write: (PTAPUE) Reset: 0 0 0 0 0 0 0 0 Read: Unimplemented Write:
$000E $0019
$001A
Read: Keyboard Status and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset: Read:
0
0
0
0
KEYF
0 ACKK
IMASKK 0 KBIE1 0
MODEK 0 KBIE0 0
0 0
0 KBIE6 0
0 KBIE5 0
0 KBIE4 0
0 KBIE3 0
0 KBIE2 0
$001B
0
$001C
Unimplemented Write:
$001D
Read: IRQ Status and Control Register Write: (INTSCR) Reset:
0
0
0
0
IRQF1
0 ACK1
IMASK1 0 R 0 STOP 0
MODE1 0 R 0 COPD 0
0
0 R 0 R 0
0 R 0 R 0
0 LVIT1 0* LVID 0
0 LVIT0 0* R 0
0 R 0 SSREC 0
$001E
Read: IRQPUD Configuration Register 2 Write: (CONFIG2) Reset: 0 Read: COPRS Configuration Register 1 Write: (CONFIG1) Reset: 0
$001F
One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only. Read: TIM Status and Control Register Write: (TSC) Reset: TOF 0 0 TOIE 0 TSTOP 1 0 TRST 0 0 R 0 PS2 0 = Reserved PS1 0 PS0 0
$0020
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Memory Map Technical Data 35
Memory Map
Addr.
Register Name Read: TIM Counter Register High Write: (TCNTH) Reset: Read: TIM Counter Register Low Write: (TCNTL) Reset: Read: TIM Counter Modulo Register High Write: (TMODH) Reset: Read: TIM Counter Modulo Register Low Write: (TMODL) Reset:
Bit 7 Bit15
6 Bit14
5 Bit13
4 Bit12
3 Bit11
2 Bit10
1 Bit9
Bit 0 Bit8
$0021
0 Bit7
0 Bit6
0 Bit5
0 Bit4
0 Bit3
0 Bit2
0 Bit1
0 Bit0
$0022
0 Bit15 1 Bit7 1 CH0F 0 0 Bit15
0 Bit14 1 Bit6 1 CH0IE 0 Bit14
0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
$0023
$0024
Read: TIM Channel 0 Status and $0025 Control Register Write: (TSC0) Reset: Read: TIM Channel 0 Register High Write: (TCH0H) Reset: Read: TIM Channel 0 Register Low Write: (TCH0L) Reset:
$0026
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0027
Indeterminate after reset CH1F 0 0 Bit15 CH1IE 0 Bit14 0 MS1A 0 Bit12 ELS1B 0 Bit11 ELS1A 0 Bit10 TOV1 0 Bit9 CH1MAX 0 Bit8
Read: TIM Channel 1 Status and $0028 Control Register Write: (TSC1) Reset: Read: TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset:
0 Bit13
$0029
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$002A
Indeterminate after reset = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
Technical Data 36 Memory Map
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr. $002B $003B
Register Name Read: Unimplemented Write:
Bit 7
6
5
4
3
2
1
Bit 0
$003C
Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset:
COCO
AIEN 0 AD6
ADCO 0 AD5
ADCH4 1 AD4
ADCH3 1 AD3
ADCH2 1 AD2
ADCH1 1 AD1
ADCH0 1 AD0
0 AD7
$003D
Indeterminate after reset ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0
Read: ADC Input Clock Register $003E Write: (ADICLK) Reset: Read: $003F Unimplemented Write:
0
0
0
0
0
$FE00
Read: Break Status Register Write: (BSR) Reset:
R
R
R
R
R
R
SBSW See note 0
R
Note: Writing a logic 0 clears SBSW. Read: Reset Status Register Write: (RSR) POR: Read: $FE02 Reserved Write: POR PIN COP ILOP ILAD MODRST LVI 0
$FE01
1 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
$FE03
Read: Break Flag Control Register Write: (BFCR) Reset:
BCFE 0 0 R 0
R
R
R
R
R
R
R
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset:
IF5 R 0
IF4 R 0
IF3 R 0
0 R 0 R
IF1 R 0 = Reserved
0 R 0
0 R 0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Memory Map Technical Data 37
Memory Map
Addr.
Register Name
Bit 7 IF14 R 0 0 R 0 R
6 0 R 0 0 R 0 R
5 0 R 0 0 R 0 R
4 0 R 0 0 R 0 R
3 0 R 0 0 R 0 R
2 0 R 0 0 R 0 R
1 0 R 0 0 R 0 R
Bit 0 0 R 0 IF15 R 0 R
Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 Write: $FE06 (INT3) Reset: Read: $FE07 Reserved Write:
$FE08
Read: FLASH Control Register Write: (FLCR) Reset: Read: FLASH Block Protect Write: Register (FLBPR) Reset: Read: Reserved Write:
0
0
0
0
HVEN 0 BPR3 0 R
MASS 0 BPR2 0 R
ERASE 0 BPR1 0 R
PGM 0 BPR0 0 R
0 BPR7 0 R
0 BPR6 0 R
0 BPR5 0 R
0 BPR4 0 R
$FE09
$FE0A $FE0B
$FE0C
Read: Break Address High Register Write: (BRKH) Reset: Read: Break Address low Register Write: (BRKL) Reset:
Bit15 0 Bit7 0 BRKE 0
Bit14 0 Bit6 0 BRKA 0
Bit13 0 Bit5 0 0
Bit12 0 Bit4 0 0
Bit11 0 Bit3 0 0
Bit10 0 Bit2 0 0
Bit9 0 Bit1 0 0
Bit8 0 Bit0 0 0
$FE0D
Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset:
0
0
0
0
0
0
$FFFF
Read: COP Control Register Write: (COPCTL) Reset:
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Technical Data 38 Memory Map MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Table 2-1. Vector Addresses
Vector Priority Lowest INT Flag -- Address $FFD0 $FFDD $FFDE $FFDF $FFE0 $FFE1 -- $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 -- $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Not Used ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) Not Used TIM Overflow Vector (High) TIM Overflow Vector (Low) TIM Channel 1 Vector (High) TIM Channel 1 Vector (Low) TIM Channel 0 Vector (High) TIM Channel 0 Vector (Low) Not Used IRQ1 Vector (High) IRQ1 Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) Vector
.
IF15 IF14 IF13 IF6 IF5 IF4 IF3 IF2 IF1 -- Highest --
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 39
Memory Map
Technical Data 40 Memory Map
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Introduction
This section describes the 128 bytes of RAM.
3.3 Functional Description
Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
NOTE:
For M6805 compatibility, the H register is not stacked.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Random-Access Memory (RAM)
Technical Data 41
Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
Technical Data 42
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Random-Access Memory (RAM) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 4. FLASH Memory (FLASH)
4.1 Contents
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 46 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Introduction
This section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
FLASH Memory Size (Bytes) 4,096 4,096 1,536
Device MC68H(R)C908JL3E MC68H(R)C908JK3E MC68H(R)C908JK1E
Memory Address Range $EC00--$FBFF $EC00--$FBFF $F600--$FBFF
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA FLASH Memory (FLASH)
Technical Data 43
FLASH Memory (FLASH)
Addr.
Register Name Read: FLASH Control Register Write: (FLCR) Reset: Read: FLASH Block Protect Register Write: (FLBPR) Reset:
Bit 7 0
6 0
5 0
4 0
3 HVEN 0 BPR3 0
2 MASS 0 BPR2 0
1 ERASE 0 BPR1 0
Bit 0 PGM 0 BPR0 0
$FE08
0 BPR7 0
0 BPR6 0
0 BPR5 0
0 BPR4 0
$FE09
= Unimplemented
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes (a page); and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: * $EC00-$FBFF; user memory; 4,096 bytes; MC68H(R)C908JL3E/JK3E $F600-$FBFF; user memory; 1,536 bytes; MC68H(R)C908JK1E $FFD0-$FFFF; user interrupt vectors; 48 bytes
*
NOTE:
An erased bit reads as logic 1 and a programmed bit reads as logic 0. A security feature prevents viewing of the FLASH contents.1
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Technical Data 44
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 FLASH Memory (FLASH) MOTOROLA
FLASH Memory (FLASH) FLASH Control Register
4.4 FLASH Control Register
The FLASH Control Register controls FLASH program and erase operations.
Address: $FE08 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 HVEN MASS ERASE PGM 3 2 1 Bit 0
Figure 4-2. FLASH Control Register (FLCR) HVEN -- High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM -- Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA FLASH Memory (FLASH)
Technical Data 45
FLASH Memory (FLASH) 4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any page within the 4K bytes user memory area ($EC00-$FBFF) can be erased alone. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH Control Register. 2. Write any data to any FLASH address within the page address range desired. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tErase (1ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh (5s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
Technical Data 46
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 FLASH Memory (FLASH) MOTOROLA
FLASH Memory (FLASH) FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH Control Register. 2. Write any data to any FLASH location within the FLASH memory address range. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tMErase (4ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA FLASH Memory (FLASH)
Technical Data 47
FLASH Memory (FLASH) 4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: (Figure 4-3 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH location within the address range of the row to be programmed. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (5s). 6. Write data to the byte being programmed. 7. Wait for time, tPROG (30s). 8. Repeat step 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5s). 11. Clear the HVEN bit. 12. After time, trcv (1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed.
NOTE:
The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum programming time, tPROG max. Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 FLASH Memory (FLASH) MOTOROLA
NOTE:
Technical Data 48
FLASH Memory (FLASH) FLASH Program Operation
1
Set PGM bit
Algorithm for programming a row (32 bytes) of FLASH memory
2
Write any data to any FLASH address within the row address range desired
3
Wait for a time, tnvs
4
Set HVEN bit
5
Wait for a time, tpgs
6
Write data to the FLASH address to be programmed
7
Wait for a time, tPROG
Completed programming this row? N
9
Y
NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
End of Programming
Figure 4-3. FLASH Programming Flowchart
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA FLASH Memory (FLASH)
Technical Data 49
FLASH Memory (FLASH) 4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH Block Protect Register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.
4.9 FLASH Block Protect Register
The FLASH Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory.
Address: $FE09 Bit 7 Read: BPR7 Write: Reset: 0 0 0 0 0 0 0 0 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 6 5 4 3 2 1 Bit 0
Figure 4-4. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Block Protect Register Bit 7 to Bit 0 BPR[7:1] represent bits [12:6] of a 16-bit memory address. Bits [15:13] are logic 1's and bits [5:0] are logic 0's.
16-bit memory address Start address of FLASH block protect 111 BPR[7:1] 000000
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
Technical Data 50
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 FLASH Memory (FLASH) MOTOROLA
FLASH Memory (FLASH) FLASH Block Protect Register
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries -- 64 bytes) within the FLASH memory. Examples of protect start address:
BPR[7:0] $00-$60 $62 or $63 (0110 001x) $64 or $65 (0110 010x) $68 or $69 (0110 100x) and so on... $DE or $DF (1101 111x) $FE (1111 1110) $FF $FBC0 (1111 1011 1100 0000) $FFC0 (1111 1111 1100 0000) The entire FLASH memory is not protected. Start of Address of Protect Range The entire FLASH memory is protected. $EC40 (1110 1100 0100 0000) $EC80 (1110 1100 1000 0000) $ED00 (1110 1101 0000 0000)
Note: The end address of the protected range is always $FFFF.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA FLASH Memory (FLASH)
Technical Data 51
FLASH Memory (FLASH)
Technical Data 52
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 FLASH Memory (FLASH) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: * * * * * * Stop mode recovery time (32 x 2OSCOUT cycles or 4096 x 2OSCOUT cycles) STOP instruction Computer operating properly module (COP) COP reset period (COPRS), (213 -24) x 2OSCOUT or (218 -24) x 2OSCOUT Enable LVI circuit Select LVI trip voltage
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Configuration Register (CONFIG)
Technical Data 53
Configuration Register (CONFIG) 5.3 Functional Description
The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytime.
NOTE:
The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 and Figure 5-2.
Address: $001E Bit 7 Read: IRQPUD Write: Reset: POR: 0 0 R 0 0 = Reserved 0 0
Not affected Not affected
6 R
5 R
4 LVIT1
3 LVIT0
2 R 0 0
1 R 0 0
Bit 0 R 0 0
0
0
Figure 5-1. Configuration Register 2 (CONFIG2) IRQPUD -- IRQ1 Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ1 pin and VDD LVIT1, LVIT0 -- Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Section 16. Low Voltage Inhibit (LVI)
Technical Data 54
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Configuration Register (CONFIG) MOTOROLA
Configuration Register (CONFIG) Functional Description
Address:
$001F Bit 7 6 R 0 = Reserved 5 R 0 4 LVID 0 3 R 0 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Read: COPRS Write: Reset: 0 R
Figure 5-2. Configuration Register 1 (CONFIG1) COPRS -- COP reset period selection bit 1 = COP reset cycle is (213 - 24) x 2OSCOUT 0 = COP reset cycle is (218 - 24) x 2OSCOUT LVID -- Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 x 2OSCOUT cycles instead of a 4096 x 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 x 2OSCOUT cycles 0 = Stop mode recovery after 4096 x 2OSCOUT cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP -- STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 15. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Configuration Register (CONFIG)
Technical Data 55
Configuration Register (CONFIG)
Technical Data 56
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Configuration Register (CONFIG) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 57
Central Processor Unit (CPU) 6.3 Features
* * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
Technical Data 58
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) CPU Registers
7 15 H 15 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
7 0 V11HINZC
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7
Read: Write: Reset: Unaffected by reset
6
5
4
3
2
1
Bit 0
Figure 6-2. Accumulator (A)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 59
Central Processor Unit (CPU)
6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Technical Data 60
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) CPU Registers
Bit 15
Read: Write: Reset: 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 6-4. Stack Pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15
Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-5. Program Counter (PC)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 61
Central Processor Unit (CPU)
6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7
Read: V Write: Reset: X X = Indeterminate 1 1 X 1 X X X 1 1 H I N Z C
6
5
4
3
2
1
Bit 0
Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
Technical Data 62 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) CPU Registers
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 63
Central Processor Unit (CPU) 6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
6.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
6.6.2 Stop Mode The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
Technical Data 64
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) CPU During Break Interrupts
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 65
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operand ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd Address Mode Opcode A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F Effect on CCR VH INZC
Operation
Description
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 - IX1 IX SP1 SP2
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
DIR INH INH -- IX1 IX SP1 DIR INH INH -- IX1 IX SP1
Arithmetic Shift Right
b7 b0
C
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn 0
Technical Data 66
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary
Cycles 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 Source Form BCS rel BEQ rel BGE opr Operand rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr Address Mode Opcode 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 Effect on CCR VH INZC Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
Operation
Description
- - - - - - REL - - - - - - REL - - - - - - REL
BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
PC (PC) + 2 +rel ? (Z) | (N V)=0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 - IX1 IX SP1 SP2
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V)=1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) = 1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 67
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Cycles 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 dd 3 1 1 1 3 2 4 Source Form Operand dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr ff ff Address Mode Opcode 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F Effect on CCR VH INZC
Operation
Description
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel
- - - - - - REL
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask
PC (PC) + 3 + rel ? (A) - (M) = $00 DIR IMM PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (X) - (M) = $00 ------ IX1+ PC (PC) + 3 + rel ? (A) - (M) = $00 IX+ PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 SP1 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
Clear
Technical Data 68
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary
Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Operand ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff dd rr rr rr ff rr rr ff rr dd ff ff Address Mode Opcode A1 B1 C1 D1 E1 F1 9EE1 9ED1 33 43 53 63 73 9E63 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 Effect on CCR VH INZC
Operation
Description
Compare A with M
(A) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
Compare H:X with M
--
Compare X with M
(X) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2
Decimal Adjust A
(A)10
U - - INH
DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV
A (A)-1 or M (M)-1 or X (X)-1 DIR PC (PC) + 3 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 - - - - - - INH IX1 PC (PC) + 3 + rel ? (result) 0 IX PC (PC) + 2 + rel ? (result) 0 SP1 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1
Decrement
--
Divide
- - - - INH
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 69
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 Source Form EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP Operand ii dd hh ll ee ff ff ff ee ff dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff Address Mode Opcode A8 B8 C8 D8 E8 F8 9EE8 9ED8 3C 4C 5C 6C 7C 9E6C BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE 38 48 58 68 78 9E68 Effect on CCR VH INZC
Operation
Description
Exclusive OR M with A
A (A M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH - IX1 IX SP1
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2 - IMM DIR
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Load H:X from M
H:X (M:M + 1)
0--
Load X from M
X (M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2
Logical Shift Left (Same as ASL)
C b7 b0
0
DIR INH INH -- IX1 IX SP1
Technical Data 70
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary
Cycles 4 1 1 4 3 5 5 4 4 4 5 dd 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 dd 4 1 1 4 3 5 Source Form LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Operand dd ff ff dd dd dd ii dd dd ff ff ff ff Address Mode Opcode 34 44 54 64 74 9E64 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 49 59 69 79 9E69 Effect on CCR VH INZC
Operation
Description
Logical Shift Right
0 b7 b0
C
DIR INH INH --0 IX1 IX SP1 DD DIX+ - IMD IX+D
(M)Destination (M)Source Move H:X (H:X) + 1 (IX+D, DIX+) Unsigned multiply X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
- 0 - - - 0 INH DIR INH INH -- IX1 IX SP1
Negate (Two's Complement)
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH -- IX1 IX SP1
Rotate Left through Carry
C b7 b0
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 71
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Cycles 4 1 1 4 3 5 1 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 Source Form ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operand dd ff ff Address Mode Opcode 36 46 56 66 76 9E66 9C 80 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF Effect on CCR VH INZC
Operation
Description
Rotate Right through Carry
b7 b0
C
DIR INH INH -- IX1 IX SP1
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 -- IX1 IX SP1 SP2
Subtract with Carry
A (A) - (M) - (C)
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2
Store X in M
M (X)
0--
Technical Data 72
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary
Cycles 2 3 4 4 3 2 4 5 9 2 1 1 dd 3 1 1 3 2 4 2 1 2 Source Form SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Operand ii dd hh ll ee ff ff ff ee ff ff ff Address Mode Opcode A0 B0 C0 D0 E0 F0 9EE0 9ED0 83 84 97 85 3D 4D 5D 6D 7D 9E6D 95 9F 94 Effect on CCR VH INZC
Operation
Description
Subtract
A (A) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
- - 1 - - - INH
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1
- - - - - - INH - - - - - - INH - - - - - - INH
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 73
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary
Cycles Source Form A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Operand Address Mode Opcode Effect on CCR VH INZC Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
Operation
Description
() -( ) #
? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
Technical Data 74
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 75
Table 6-2. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
DIR 3
INH 4
Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
SP1 9E6
IX 7
Control INH INH 8 9
IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM
DIR B
EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT
Register/Memory IX2 SP2 D 4 SUB IX2 4 CMP IX2 4 SBC IX2 4 CPX IX2 4 AND IX2 4 BIT IX2 4 LDA IX2 4 STA IX2 4 EOR IX2 4 ADC IX2 4 ORA IX2 4 ADD IX2 4 JMP IX2 6 JSR IX2 4 LDX IX2 4 STX IX2 9ED 5 SUB SP2 5 CMP SP2 5 SBC SP2 5 CPX SP2 5 AND SP2 5 BIT SP2 5 LDA SP2 5 STA SP2 5 EOR SP2 5 ADC SP2 5 ORA SP2 5 ADD SP2
IX1 E
SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1
IX F
0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4 5 6 7 8 9 A B C D E F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4
4 4
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX SP2 2 IX1 5 3 STX STX SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
Central Processor Unit (CPU) Opcode Map
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
Technical Data 76
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Central Processor Unit (CPU) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 7. System Integration Module (SIM)
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 81 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 81 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 83 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 85 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 86 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 86 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .87 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 94
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 77
System Integration Module (SIM)
7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 100
7.2 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - Stop/wait/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
Technical Data 78
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
2OSCOUT (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR)
/2
VDD CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS
INTERNAL PULL-UP
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 7-1. SIM Block Diagram Table 7-1. Signal Name Conventions
Signal Name 2OSCOUT OSCOUT IAB IDB PORRST IRST R/W Description Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit. The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT / 4) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 79
System Integration Module (SIM)
Addr.
Register Name Read: Break Status Register Write: (BSR) Reset:
Bit 7 R 0
6 R 0
5 R 0
4 R 0
3 R 0
2 R
1 SBSW
Bit 0 R
$FE00
NOTE 0 0 0
Note: Writing a logic 0 clears SBSW. Read: $FE01 Reset Status Register Write: (RSR) POR: Read: R $FE02 Reserved Write: Reset: Read: Break Flag Control Register Write: (BFCR) Reset: Read: $FE04 Interrupt Status Register 1 Write: (INT1) Reset: Read: $FE05 Interrupt Status Register 2 Write: (INT2) Reset: Read: $FE06 Interrupt Status Register 3 Write: (INT3) Reset: BCFE 0 0 R 0 IF14 R 0 0 R 0 IF5 R 0 0 R 0 0 R 0 IF4 R 0 0 R 0 0 R 0 IF3 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 R IF1 R 0 0 R 0 0 R 0 = Reserved 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 IF15 R 0 R R R R R R R R R R R R R R POR PIN COP ILOP ILAD MODRST LVI 0
1
0
0
0
0
0
0
0
$FE03
= Unimplemented
Figure 7-2. SIM I/O Register Summary
Technical Data 80
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) SIM Bus Clock Control and Generation
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 7-3.
From OSCILLATOR From OSCILLATOR
2OSCOUT OSCOUT
SIM COUNTER
/2
BUS CLOCK GENERATORS
SIM
Figure 7-3. SIM Clock Signals 7.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four. 7.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the time-out. 7.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 7.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 81
System Integration Module (SIM) 7.4 Reset and System Initialization
The MCU has these reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address
All of these resets produce the vector $FFFE-$FFFF ($FEFE-$FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 7.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 7.8 SIM Registers.) 7.4.1 External Pin Reset The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 2OSCOUT cycles, assuming that the POR was not the source of the reset. See Table 7-2 for details. Figure 7-4 shows the relative timing. Table 7-2. PIN Bit Set Timing
Reset Type POR All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
2OSCOUT RST IAB PC VECT H VECT L
Figure 7-4. External Reset Timing
Technical Data 82 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Reset and System Initialization
7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 7-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 7-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 2OSCOUT cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-5.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
2OSCOUT
IAB
VECTOR HIGH
Figure 7-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET
Figure 7-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 83
System Integration Module (SIM)
7.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive 2OSCOUT. Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES 2OSCOUT 32 CYCLES 32 CYCLES
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 7-7. POR Recovery
Technical Data 84
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Reset and System Initialization
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every (212 - 24) 2OSCOUT cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. The COP module is disabled if the RST pin or the IRQ1 pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ1 pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VDD + VHI on the RST pin disables the COP module.
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources.
7.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 85
System Integration Module (SIM)
7.4.2.5 LVI Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixtyfour 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RSTB) pin for all internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of 2OSCOUT.
7.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.
7.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
Technical Data 86 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Exception Control
7.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 7.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
7.6 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts
7.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 7-8 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared).
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 87
System Integration Module (SIM)
FROM RESET
BREAK INTERRUPT? I BIT SET? NO
YES
YES
I BIT SET?
NO
IRQ INTERRUPT? NO
YES
TIMER INTERRUPT? NO (As many interrupts as exist on chip)
YES
STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
Figure 7-8. Interrupt Processing
Technical Data 88
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Exception Control
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-9 shows interrupt entry timing. Figure 7-10 shows interrupt recovery timing.
MODULE INTERRUPT I BIT
IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 7-9. Interrupt Entry
MODULE INTERRUPT I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[15:8] PC - 1[7:0]
OPCODE
OPERAND
R/W
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 89
System Integration Module (SIM)
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 7-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
Technical Data 90
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Exception Control
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
7.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.
Table 7-3. Interrupt Sources
Priority Highest Reset SWI Instruction IRQ1 Pin Timer Channel 0 Interrupt Timer Channel 1 Interrupt Timer Overflow Interrupt Keyboard Interrupt Lowest ADC Conversion Complete Interrupt Source Flag -- -- IRQF1 CH0F CH1F TOF KEYF COCO Mask1(1) -- -- IMASK1 CH0IE CH1IE TOIE IMASKK AIEN INT Register Flag -- -- IF1 IF3 IF4 IF5 IF14 IF15 Vector Address $FFFE-$FFFF $FFFC-$FFFD $FFFA-$FFFB $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFE0-$FFE1 $FFDE-$FFDF
Notes: 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 91
System Integration Module (SIM)
7.6.2.1 Interrupt Status Register 1
Address: $FE04 Bit 7 Read: Write: Reset: 0 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 0 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 7-12. Interrupt Status Register 1 (INT1) IF1, IF3 to IF5 -- Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3 and 7 -- Always read 0
7.6.2.2 Interrupt Status Register 2
Address: $FE05 Bit 7 Read: Write: Reset: IF14 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 0 R 0
Figure 7-13. Interrupt Status Register 2 (INT2) IF14 -- Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 to 6 -- Always read 0
Technical Data 92
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Exception Control
7.6.2.3 Interrupt Status Register 3
Address: $FE06 Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 IF15 R 0
Figure 7-14. Interrupt Status Register 3 (INT3) IF15 -- Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1 to 7 -- Always read 0
7.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated.
7.6.4 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 17. Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 93
System Integration Module (SIM)
7.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
7.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 7-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Technical Data 94 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) Low-Power Modes
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 7-15. Wait Mode Entry Timing Figure 7-16 and Figure 7-17 show the timing for WAIT recovery.
IAB $6E0B $6E0C $00FF $00FE $00FD $00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-16. Wait Recovery from Interrupt or Break
32 Cycles IAB $6E0B
32 Cycles RST VCTH RSTVCTL
IDB
$A6
$A6
$A6
RST
2OSCOUT
Figure 7-17. Wait Recovery from Internal Reset
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 95
System Integration Module (SIM)
7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 7-18. Stop Mode Entry Timing
Technical Data 96
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) SIM Registers
STOP RECOVERY PERIOD 2OSCOUT
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 7-19. Stop Mode Recovery from Interrupt or Break
7.8 SIM Registers
The SIM has three memory mapped registers. Table 7-4 shows the mapping of these registers. Table 7-4. SIM Registers
Address $FE00 $FE01 $FE03 Register BSR RSR BFCR Access Mode User User User
7.8.1 Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address: $FE00 Bit 7 Read: R Write: Reset: R = Reserved R R R R R 6 5 4 3 2 1 SBSW Note(1) 0 1. Writing a logic zero clears SBSW. R Bit 0
Figure 7-20. Break Status Register (BSR)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 97
System Integration Module (SIM)
SBSW -- SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,BSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited ; by break. ; If RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register.
7.8.2 Reset Status Register (RSR) This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Technical Data 98
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM) SIM Registers
Address:
$FE01 Bit 7 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Read: Write: POR:
POR
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-21. Reset Status Register (RSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST -- Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ1 = VDD 0 = POR or read of SRSR LVI -- Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 99
System Integration Module (SIM)
7.8.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address:
$FE03 Bit 7 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Read: BCFE Write: Reset: 0 R = Reserved
Figure 7-22. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Technical Data 100
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 8. Oscillator (OSC)
8.1 Contents
8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E). . . . . . . . . . . 102 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . 103
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 104 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . 104 8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 104 8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . 104 8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . 105 8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 106
8.2 Introduction
The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available: * MC68HC908JL3E/JK3E/JK1E -- built-in oscillator module (X-tal) that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1. MC68HRC908JL3E/JK3E/JK1E -- built-in oscillator module (RC) that requires an external RC connection only.
*
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Oscillator (OSC)
Technical Data 101
Oscillator (OSC) 8.3 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E)
The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 8-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional)
To SIM 2OSCOUT To SIM OSCOUT
From SIM
XTALCLK SIMOSCEN
/2
MCU
OSC1 RB OSC2
R S* X1 *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data. See Section 18. for component value requirements. C1 C2
Figure 8-1. X-tal Oscillator External Connections
Technical Data 102 Oscillator (OSC)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Oscillator (OSC) RC Oscillator (MC68HRC908JL3E/JK3E/JK1E)
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information.
8.4 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E)
The RC oscillator circuit is designed for use with external R and C to provide a clock source with tolerance less than 10%. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: * * CEXT REXT
To SIM 2OSCOUT To SIM OSCOUT
From SIM
SIMOSCEN
EN
Ext-RC Oscillator
RCCLK
/2
0 PTA6 I/O
1
PTA6 PTA6EN
MCU
OSC1 PTA6/RCCLK (OSC2)
VDD
REXT
CEXT
See Section 18. for component value requirements.
Figure 8-2. RC Oscillator External Connections
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Oscillator (OSC)
Technical Data 103
Oscillator (OSC) 8.5 I/O Signals
The following paragraphs describe the oscillator I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.
8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK) For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier. For the RC oscillator device, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the internal RC oscillator clock, RCCLK.
Device MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Oscillator X-tal RC OSC2 pin function Inverting OSC1 Controlled by PTA6EN bit in PTAPUER ($0D) PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6 I/O
8.5.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the X-tal oscillator circuit or the RC-oscillator.
8.5.4 X-tal Oscillator Clock (XTALCLK) XTALCLK is the X-tal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 8-1 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up.
Technical Data 104 Oscillator (OSC) MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Oscillator (OSC) Low Power Modes
8.5.5 RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 8-2 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.
8.5.6 Oscillator Out 2 (2OSCOUT) 2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module and is used to determine the COP cycles.
8.5.7 Oscillator Out (OSCOUT) The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.
8.6 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
8.6.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module.
8.6.2 Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Oscillator (OSC)
Technical Data 105
Oscillator (OSC) 8.7 Oscillator During Break Mode
The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state.
Technical Data 106 Oscillator (OSC)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 9. Monitor ROM (MON)
9.1 Contents
9.2 9.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.4.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, VDD + VHI, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 107
Monitor ROM (MON) 9.3 Features
Features of the monitor ROM include the following: * * * * * * * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in RAM or FLASH FLASH memory security feature1 FLASH memory programming interface 960 bytes monitor ROM code size Monitor mode entry without high voltage, VDD + VHI, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage, VDD + VHI, is applied to IRQ1
9.4 Functional Description
The monitor ROM receives and executes commands from a host computer. Figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
Technical Data 108 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Functional Description
RC CIRCUIT FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION B
VDD See Figure 18-1 for component values vs. frequency.
RST 0.1 F
OSC1 OSC2
H(R)C908JL3E H(R)C908JK3E H(R)C908JK1E
VDD VDD 0.1 F VSS
EXT OSC FOR MC68HC908JL3E/JK3E/JK1E SW1 AT POSITION A OR B FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION A
VDD
(50% DUTY) OSC1 OSC2
XTAL CIRCUIT FOR MC68HC908JL3E/JK3E/JK1E SW1 AT POSITION A OR B MAX232 1 1 F + 3 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 2 74HC125 3 1 V- 6 + 1 F 74HC125 5 6 4 10 k C1+ VCC 16 + 15 + 2 1 F 1 F VDD + VHI VDD VDD 20 pF
9.8304MHz 10M
OSC1
OSC2 20 pF
C1- C2+
GND V+
A 1k 8.5 V B
SW1
(SEE NOTE 1) IRQ VDD
10 k
PTB0 VDD 10 k C SW2 VDD 10 k PTB1 PTB3 D 10 k 10 k PTB2
NOTES: 1. Monitor mode entry method: SW1: Position A -- High voltage entry (VTST) Clock source must be EXT OSC or XTAL CIRCUIT. Bus clock depends on SW2. SW1: Position B -- Reset vector must be blank ($FFFE = $FFFF = $FF) Bus clock = OSC1 / 4. 2. Affects high voltage entry to monitor mode only (SW1 at position A): SW2: Position C -- Bus clock = OSC1 / 4 SW2: Position D -- Bus clock = OSC1 / 2 5. See Table 18-4 for VDD + VHI voltage level requirements.
(SEE NOTE 2)
Figure 9-1. Monitor Mode Circuit
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON) Technical Data 109
Monitor ROM (MON)
9.4.1 Entering Monitor Mode Table 9-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If IRQ1 = VDD + VHI: - Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL) - PTB3 = low 2. If IRQ1 = VDD + VHI: - Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL) - PTB3 = high 3. If $FFFE & $FFFF is blank (contains $FF): - Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC) - IRQ1 = VDD Table 9-1. Monitor Mode Entry Requirements and Options
PTB3(1) $FFFE and $FFFF PTB2 PTB1 PTB0 IRQ1 OSC1 Frequency Bus Frequency 2.4576MHz (OSC1 / 2) 2.4576MHz (OSC1 / 4) 2.4576MHz (OSC1 / 4) OSC1 / 4 Comments High-voltage entry to monitor mode.(3) 9600 baud communication on PTB0. COP disabled. Low-voltage entry to monitor mode.(4) 9600 baud communication on PTB0. COP disabled. Enters User mode.
VDD + VHI(2) VDD + VHI
X X BLANK (contain $FF) NOT BLANK
0 1
0 0
1 1
1 1
4.9152MHz 9.8304MHz
VDD
X
X
X
1
9.8304MHz At desired frequency
VDD
X
X
X
X
Notes: 1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VDD + VHI for monitor mode entry. The OSC1 clock must be 50% duty cycle for this condition. 2. See Table 18-4 for VDD + VHI voltage level requirements. 3. For IRQ1 = VDD + VHI: MC68HRC908JL3E/JK3E/JK1E -- clock must be EXT OSC. MC68HC908JL3E/JK3E/JK1E -- clock can be EXT OSC or XTAL. 4. For IRQ1 = VDD: MC68HRC908JL3E/JK3E/JK1E -- clock must be RC OSC. MC68HC908JL3E/JK3E/JK1E -- clock can be EXT OSC or XTAL.
Technical Data 110 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Functional Description
If VDD +VHI is applied to IRQ1 and PTB3 is low upon monitor mode entry (Table 9-1 condition set 1), the bus frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VDD +VHI applied to IRQ1 upon monitor mode entry (Table 9-1 condition set 2), the bus frequency is a divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VDD +VHI is applied to IRQ1. In this event, the OSCOUT frequency is equal to the 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. Entering monitor mode with VDD + VHI on IRQ1, the COP is disabled as long as VDD + VHI is applied to either the IRQ1 or the RST. (See Section 7. System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ1 and reset vector being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions, including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ1 or the RST. Figure 9-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ1 = VDD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 111
Monitor ROM (MON)
POR RESET
IS VECTOR BLANK? YES
NO
NORMAL USER MODE
MONITOR MODE
EXECUTE MONITOR CODE
POR TRIGGERED?
NO
YES
Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 9.5 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate. In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code.
Technical Data 112 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Functional Description
Table 9-2 is a summary of the vector differences between user mode and monitor mode. Table 9-2. Monitor Mode Vector Differences
Functions Modes COP Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
User Monitor
Notes: 1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer.
9.4.2 Baud Rate The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ1 = VDD + VHI. When PTB3 is high, the divide by ratio is 1024. If the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 9-3. Monitor Baud Rate Selection
Monitor Mode Entry By: Input Clock Frequency 4.9152 MHz IRQ1 = VDD + VHI 9.8304 MHz 4.9152 MHz Blank reset vector, IRQ1 = VDD 9.8304 MHz 4.9152 MHz PTB3 0 1 1 X X Baud Rate 9600 bps 9600 bps 4800 bps 9600 bps 4800 bps
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 113
Monitor ROM (MON)
9.4.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 9-3 and Figure 9-4.)
NEXT START BIT
START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 9-3. Monitor Data Format
NEXT START BIT NEXT START BIT
$A5 BREAK
START BIT START BIT
BIT 0 BIT 0
BIT 1 BIT 1
BIT 2 BIT 2
BIT 3 BIT 3
BIT 4 BIT 4
BIT 5 BIT 5
BIT 6 BIT 6
BIT 7 BIT 7
STOP BIT STOP BIT
Figure 9-4. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical.
9.4.4 Echoing As shown in Figure 9-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking.
SENT TO MONITOR READ ECHO READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
RESULT
Figure 9-5. Read Transaction Any result of a command appears after the echo of the last byte of the command.
Technical Data 114 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Functional Description
9.4.5 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 9-6.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-6. Break Transaction 9.4.6 Commands The monitor ROM uses the following commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 115
Monitor ROM (MON)
Table 9-4. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A
Command Sequence
SENT TO MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Table 9-5. WRITE (Write Memory) Command
Description Operand Data Returned Opcode Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49
Command Sequence
SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
ECHO
Technical Data 116 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Functional Description
Table 9-6. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A
Command Sequence
SENT TO MONITOR IREAD IREAD DATA DATA
ECHO
RESULT
Table 9-7. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Specifies single data byte None $19
Command Sequence
SENT TO MONITOR IWRITE IWRITE DATA DATA
ECHO
NOTE:
A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 117
Monitor ROM (MON)
Table 9-8. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C
Command Sequence
SENT TO MONITOR READSP READSP SP HIGH SP LOW
ECHO
RESULT
Table 9-9. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes RTI instruction None None $28
Command Sequence
SENT TO MONITOR RUN RUN
ECHO
Technical Data 118 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Monitor ROM (MON) Security
9.5 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain userdefined data.
NOTE:
Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 9-7.)
VDD 4096 + 32 OSCXCLK CYCLES RST 24 BUS CYCLES COMMAND 1 BYTE 8 ECHO BYTE 2 ECHO 2 4 1 COMMAND ECHO BREAK BYTE 1 BYTE 2 BYTE 8 1
FROM HOST
PTB0 1 BYTE 1 ECHO FROM MCU 4
NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte.
Figure 9-7. Monitor Mode Entry Timing
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Monitor ROM (MON)
Technical Data 119
Monitor ROM (MON)
Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
Technical Data 120 Monitor ROM (MON)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 10. Timer Interface Module (TIM)
10.1 Contents
10.2 10.3 10.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 126 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 127 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 127 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 128 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 129 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.8 10.9 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .134 10.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 136 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 137 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) .138 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 142
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 121
Timer Interface Module (TIM) 10.2 Introduction
This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 is a block diagram of the TIM.
10.3 Features
Features of the TIM include the following: * Two input capture/output compare channels - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * * * * * Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIM clock input with 7-frequency internal bus clock prescaler selection Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
10.4 Pin Name Conventions
The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in Table 10-1. The generic pin name appear in the text that follows. Table 10-1. Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: TCH0 PTD4/TCH0 TCH1 PTD5/TCH1
Technical Data 122
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) Functional Description
10.5 Functional Description
Figure 10-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels.
PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0
Figure 10-1. TIM Block Diagram
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 123
Timer Interface Module (TIM)
Addr.
Register Name TIM Status and Control Register (TSC) Read: Write: Reset: Read:
Bit 7 TOF
6 TOIE
5 TSTOP
4 0 TRST
3 0
2 PS2
1 PS1 0 Bit9
Bit 0 PS0 0 Bit8
$0020
0 0 Bit15 0 Bit14 1 Bit13
0 Bit12
0 Bit11
0 Bit10
$0021
TIM Counter Register High (TCNTH)
Write: Reset: Read: 0 Bit7 0 Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0
$0022
TIM Counter Register Low (TCNTL)
Write: Reset: 0 Bit15 Write: Reset: Read: Bit7 Write: Reset: Read: Write: Reset: Read: Bit15 Write: Reset: Read: Bit7 Write: Reset: Read: Write: Reset: CH1F CH1IE 0 0 0 0 0 0 0 0 0 0 MS1A ELS1B ELS1A TOV1
CH1MAX
0 Bit14 1 Bit6 1 CH0IE
0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 1 Bit0 1
CH0MAX
$0023
TIM Counter Modulo Register High (TMODH)
Read:
1
$0024
TIM Counter Modulo Register Low (TMODL)
1 CH0F 0 0
$0025
TIM Channel 0 Status and Control Register (TSC0)
0 Bit14
0 Bit8
$0026
TIM Channel 0 Register High (TCH0H)
Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0027
TIM Channel 0 Register Low (TCH0L)
Indeterminate after reset
$0028
TIM Channel 1 Status and Control Register (TSC1)
Figure 10-2. TIM I/O Register Summary
Technical Data 124 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) Functional Description
$0029
TIM Channel 1 Register High (TCH1H)
Read: Bit15 Write: Reset: Read: Bit7 Write: Reset: = Unimplemented Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Indeterminate after reset Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
$002A
TIM Channel 1 Register Low (TCH1L)
Figure 10-2. TIM I/O Register Summary 10.5.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.
10.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
10.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 125
Timer Interface Module (TIM)
10.5.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
Technical Data 126
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) Functional Description
10.5.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
10.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 10-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM to set the pin if the state of the PWM pulse is logic zero.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 127
Timer Interface Module (TIM)
OVERFLOW PERIOD OVERFLOW OVERFLOW
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 10.10.1 TIM Status and Control Register (TSC)). The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.
10.5.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 10.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.
Technical Data 128 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) Functional Description
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 129
Timer Interface Module (TIM)
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
10.5.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 10-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 10-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Technical Data 130
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).)
10.6 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1. CHxF and CHxIE are in the TIM channel x status and control register.
*
10.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
10.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
10.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
10.8 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR).) To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.
Technical Data 132
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) I/O Signals
10.9 I/O Signals
Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.
10.10 I/O Registers
The following I/O registers control and monitor operation of the TIM: * * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
10.10.1 TIM Status and Control Register (TSC) The TIM status and control register does the following: * * * * *
Address:
Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
$0020 Bit 7 6 TOIE 5 TSTOP TRST 0 1 0 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
Read: Write: Reset:
TOF 0 0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic zero to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic one to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled
Technical Data 134 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) I/O Registers
TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic zero. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 10-2 shows. Reset clears the PS[2:0] bits. Table 10-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal Bus Clock / 1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 Not available
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
10.10.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: $0021 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit15 TCNTH 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8
Address:
$0022 Bit 7
TCNTL 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0
Read: Write: Reset:
Bit7
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
Technical Data 136
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) I/O Registers
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023 Bit 7 Read: Bit15 Write: Reset: 1 1 1 1 1 1 1 1 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TMODH 6 5 4 3 2 1 Bit 0
Address:
$0024 Bit 7
TMODL 6 Bit6 1 5 Bit5 1 4 Bit4 1 3 Bit3 1 2 Bit2 1 1 Bit1 1 Bit 0 Bit0 1
Read: Bit7 Write: Reset: 1
Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: * * * * * * * *
Address:
Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
$0025 Bit 7 TSC0 6 CH0IE 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0
CH0MAX
Read: Write: Reset:
CH0F 0 0 0 0
Address:
$0028 Bit 7
TSC1 6 CH1IE 5 0 MS1A 0 0 ELS1B 0 ELS1A 0 TOV1 0
CH1MAX
4
3
2
1
Bit 0
Read: Write: Reset:
CH1F 0 0 0
0
= Unimplemented
Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1)
Technical Data 138
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) I/O Registers
CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 10-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 139
Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 10-3.) Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 10-3. Mode, Edge, and Level Selection
MSxB
X X 0 0 0 0 0 0 1 1 1
MSxA
0 1 0 0 0 1 1 1 X X X
ELSxB
0 0 0 1 1 0 1 1 0 1 1
ELSxA
0
Mode
Configuration
Pin under Port Control; Initial Output Level High Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only
Output Preset 0 1 0 1 1 0 1 1 0 1 Output Compare or PWM Input Capture
Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare
Buffered Toggle Output on Compare Output Compare or Clear Output on Compare Buffered Set Output on Compare PWM
Technical Data 140
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM) I/O Registers
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic one, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD OVERFLOW OVERFLOW OVERFLOW OVERFLOW
TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-8. CHxMAX Latency
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026 Bit 7 Read: Bit15 Write: Reset: Address: $0027 Bit 7 Read: Bit7 Write: Reset: Address: $0029 Bit 7 Read: Bit15 Write: Reset: Address: $02A Bit 7 Read: Bit7 Write: Reset: Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCH1L 6 5 4 3 2 1 Bit 0 Indeterminate after reset Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCH1H 6 5 4 3 2 1 Bit 0 Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCH0L 6 5 4 3 2 1 Bit 0 Indeterminate after reset Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCH0H 6 5 4 3 2 1 Bit 0
Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Technical Data 142 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Timer Interface Module (TIM) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 11. Analog-to-Digital Converter (ADC)
11.1 Contents
11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 148 11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.2 Introduction
This section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter (ADC).
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC)
Technical Data 143
Analog-to-Digital Converter (ADC) 11.3 Features
Features of the ADC module include: * * * * * * 12 channels with multiplexed input Linear successive approximation with monotonicity 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock
Addr.
Register Name Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset:
Bit 7 COCO
6 AIEN 0 AD6
5 ADCO 0 AD5
4 ADCH4 1 AD4
3 ADCH3 1 AD3
2 ADCH2 1 AD2
1 ADCH1 1 AD1
Bit 0 ADCH0 1 AD0
$003C
0 AD7
$003D
Indeterminate after reset ADIV2 0 ADIV1 0 ADIV0 0 0 0 0 0 0
Read: ADC Input Clock Register $003E Write: (ADICLK) Reset:
0
0
0
0
0
Figure 11-1. ADC I/O Register Summary
11.4 Functional Description
Twelve ADC channels are available for sampling external sources at pins PTB0-PTB7 and PTD0-PTD3. An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 11-2 shows a block diagram of the ADC.
Technical Data 144
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Analog-to-Digital Converter (ADC) MOTOROLA
Analog-to-Digital Converter (ADC) Functional Description
INTERNAL DATA BUS READ DDRB/DDRD DISABLE RESET WRITE PTB/PTD PTBx/PTDx ADCx DDRBx/DDRDx
WRITE DDRB/DDRD
READ PTB/PTD
DISABLE ADC CHANNEL x ADC DATA REGISTER
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC
ADC VOLTAGE IN ADCVIN
CHANNEL SELECT (1 OF 12 CHANNELS)
ADCH[4:0]
AIEN
COCO
ADC CLOCK
BUS CLOCK
CLOCK GENERATOR
ADIV[2:0]
ADICLK
Figure 11-2. ADC Block Diagram
11.4.1 ADC Port I/O Pins PTB0-PTB7 and PTD0-PTD3 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Technical Data 145
Analog-to-Digital Converter (ADC)
Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
11.4.2 Voltage Conversion When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE:
Input voltage should not exceed the analog supply voltages.
11.4.3 Conversion Time Fourteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1MHz, then one conversion will take 14s to complete. With a 1MHz ADC internal clock the maximum sample rate is 71.43kHz. 14 ADC Clock Cycles ADC Clock Frequency
Conversion Time =
Number of Bus Cycles = Conversion Time x Bus Frequency 11.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADC status and control register, $003C) is set after each conversion and can be cleared by writing the ADC status and control register or reading of the ADC data register.
Technical Data 146 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Analog-to-Digital Converter (ADC) MOTOROLA
Analog-to-Digital Converter (ADC) Interrupts
11.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes.
11.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
11.6 Low-Power Modes
The following subsections describe the ADC in low-power modes.
11.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1's before executing the WAIT instruction.
11.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode.
11.7 I/O Signals
The ADC module has 12 channels that are shared with I/O port B and port D.
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11.7.1 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module.
11.8 I/O Registers
These I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK)
11.8.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register.
Address: $003C Bit 7 Read: Write: Reset: 0 0 0 1 1 1 1 1 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 11-3. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read. Reset clears this bit. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be logic 0 when read.
Technical Data 148 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Analog-to-Digital Converter (ADC) MOTOROLA
Analog-to-Digital Converter (ADC) I/O Registers
AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select bits are detailed in the following table. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (See Table 11-1.) The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a logic 1.
NOTE:
Recovery from the disabled state requires one conversion cycle to stabilize.
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Table 11-1. MUX Channel Select
ADCH4 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 1 1 1 1 1 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 : 1 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 : 0 0 1 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 : 1 1 0 0 1 1 ADCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 : 0 1 0 1 0 1 -- -- Reserved Unused VDDA (see Note 2) VSSA (see Note 2) ADC power off -- Unused (see Note 1) ADC Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 Input Select PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTD3 PTD2 PTD1 PTD0
NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.
Technical Data 150
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Analog-to-Digital Converter (ADC) I/O Registers
11.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003D Bit 7 Read: Write: Reset: = Unimplemented Indeterminate after reset AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
Figure 11-4. ADC Data Register (ADR)
11.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
Address: $003E Bit 7 Read: ADIV2 Write: Reset:
0
6 ADIV1 0
5 ADIV0 0
4 0
3 0
2 0
1 0
Bit 0 0
0
0
0
0
0
= Unimplemented
Figure 11-5. ADC Input Clock Register (ADICLK) ADIV[2:0] -- ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 11-2 shows the available clock configurations. The ADC clock should be set to approximately 1MHz.
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Table 11-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 X = don't care ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC Input Clock / 1 ADC Input Clock / 2 ADC Input Clock / 4 ADC Input Clock / 8 ADC Input Clock / 16
Technical Data 152
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Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 12. Input/Output (I/O) Ports
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 157 12.3.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . 158 12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 160 12.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 162 12.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 163 12.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 164
12.2 Introduction
Twenty three (23) bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
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Technical Data 153
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Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read:
Bit 7 0
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset 0 DDRA6 0 0 DDRB6 0 DDRD6 0 0 DDRA5 0 DDRB5 0 DDRD5 0 0 DDRA4 0 DDRB4 0 DDRD4 0 0 SLOWD7 SLOWD6 PTDPU7 0 0 0 0 0 0 0 PTDPU6 0 DDRA3 0 DDRB3 0 DDRD3 0 DDRA2 0 DDRB2 0 DDRD2 0 DDRA1 0 DDRB1 0 DDRD1 0 DDRA0 0 DDRB0 0 DDRD0 0
$0004
$0005
DDRB7 Data Direction Register B Write: (DDRB) Reset: 0 Read: DDRD7 Data Direction Register D Write: (DDRD) Reset: 0 Read: 0 Port D Control Register Write: (PDCR) Reset:
$0007
$000A
$000D
Read: Port A Input Pull-up PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Enable Register Write: (PTAPUE) Reset: 0 0 0 0 0 0 0 0
Figure 12-1. I/O Port Register Summary
Technical Data 154 Input/Output (I/O) Ports
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Input/Output (I/O) Ports Introduction
Table 12-1. Port Control Register Bits Summary
Module Control Port Bit 0 1 2 A 3 4 5 6 0 1 2 3 B 4 5 6 7 0 1 2 3 D 4 5 6 7 DDRD4 TIM DDRD5 DDRD6 DDRD7 -- -- TSC1 ($0028) -- -- ELS1B:ELS1A -- -- PTD5/TCH1 PTD6 PTD7 TSC0 ($0025) ELS0B:ELS0A PTD4/TCH0 DDRB4 DDRB5 DDRB6 DDRB7 DDRD0 DDRD1 ADC DDRD2 DDRD3 ADSCR ($003C) ADCH[4:0] PTD2/ADC9 PTD3/ADC8 DDR Module DDRA0 DDRA1 DDRA2 KBI DDRA3 DDRA4 DDRA5 DDRA6 DDRB0 DDRB1 DDRB2 DDRB3 ADC ADSCR ($003C) ADCH[4:0] PTB4/ADC4 PTB5/ADC5 PTB6/ADC6 PTB7/ADC7 PTD0/ADC11 PTD1/ADC10 OSC KBI PTAPUE ($000D) KBIER ($001B) KBIER ($001B) KBIE3 KBIE4 KBIE5 PTA6EN KBIE6 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 RCCLK/PTA6/KBI6(1) PTB0/ADC0 PTB1/ADC1 PTB2/ADC2 PTB3/ADC3 Register Control Bit KBIE0 KBIE1 KBIE2 PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 Pin
Notes: 1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option); PTAPUE register has priority control over the port pin. RCCLK/PTA6/KBI6 is the OSC2 pin on MC68HC908JL3E/JK3E/JK1E devices (X-TAL option).
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Input/Output (I/O) Ports 12.3 Port A
Port A is an 7-bit special function port that shares all seven of its pins with the keyboard interrupt (KBI) module (see Section 14. Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable pull-up device if the corresponding port pin is configured as input port. PTA0 to PTA5 has direct LED drive capability.
NOTE:
PTA0-PTA5 pins are available on MC68H(R)C908JL3E only. PTA6 pin is available on MC68HRC908JL3E/JK3E/JK1E only.
12.3.1 Port A Data Register (PTA) The port A data register (PTA) contains a data latch for each of the seven port A pins.
Address: $0000 Bit 7 Read: Write: Reset: Additional Functions: LED (Sink) Unaffected by Reset LED (Sink) LED (Sink) LED (Sink) LED (Sink) LED (Sink) 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 6 5 4 3 2 1 Bit 0
30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up
Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Figure 12-2. Port A Data Register (PTA) PTA[6:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[6:0] -- Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE[6:0], in the keyboard interrupt control register (KBIER) enable the port A pins as external interrupt pins, (see Section 14. Keyboard Interrupt Module (KBI)).
Technical Data 156 Input/Output (I/O) Ports MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Input/Output (I/O) Ports Port A
12.3.2 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer.
Address: $0004 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0
Figure 12-3. Data Direction Register A (DDRA) DDRA[6:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004) PTAPUEx WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx 30k
READ PTA ($0000)
To Keyboard Interrupt Circuit
Figure 12-4. Port A I/O Circuit
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When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
12.3.3 Port A Input Pull-up Enable Register (PTAPUE) The port A input pull-up enable register (PTAPUE) contains a software configurable pull-up device for each of the seven port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output.
Address: $000D Bit 7 Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 12-5. Port A Input Pull-up Enable Register (PTAPUE) PTA6EN -- Enable PTA6 on OSC2 This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has no effect for X-tal oscillator option. 1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions 0 = OSC2 pin outputs the RC oscillator clock (RCCLK) PTAPUE[6:0] -- Port A Input Pull-up Enable Bits These read/write bits are software programmable to enable pull-up devices on port A pins 1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0 0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit
Technical Data 158 Input/Output (I/O) Ports MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Input/Output (I/O) Ports Port B
Table 12-2 summarizes the operation of the port A pins. Table 12-2. Port A Pin Functions
PTAPUE Bit DDRA Bit Accesses to DDRA PTA Bit I/O Pin Mode Read/Write Read Write Accesses to PTA
1 0 X
0 0 1
X(1) X X
Input, VDD(2) Input, Hi-Z(4) Output
DDRA[6:0] DDRA[6:0] DDRA[6:0]
Pin Pin PTA[6:0]
PTA[6:0](3) PTA[6:0](3) PTA[6:0]
Notes: 1. X = Don't care. 2. I/O pin pulled to VDD by internal pull-up. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High Impedance.
12.4 Port B
Port B is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (ADC) module, see Section 11. 12.4.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins.
Address: $0001 Bit 7 Read: PTB7 Write: Reset: Alternative Function: ADC7 ADC6 ADC5 Unaffected by reset ADC4 ADC3 ADC2 ADC2 ADC0 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 6 5 4 3 2 1 Bit 0
Figure 12-6. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.
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ADC[7:0] -- ADC channels 7 to 0 ADC[7:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Section 11. Analog-to-Digital Converter (ADC).
12.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer.
Address: $0005 Bit 7 Read: DDRB7 Write: Reset: 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 6 5 4 3 2 1 Bit 0
Figure 12-7. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic.
Technical Data 160 Input/Output (I/O) Ports
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Input/Output (I/O) Ports Port D
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
To Analog-To-Digital Converter
Figure 12-8. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins. Table 12-3. Port B Pin Functions
Accesses to DDRB DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z Output
(2)
Accesses to PTB Read Pin Pin Write PTB[7:0](3) PTB[7:0]
DDRB[7:0] DDRB[7:0]
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
12.5 Port D
Port D is an 8-bit special function port that shares two of its pins with timer interface module, (see Section 10.) and shares four of its pins with analog-to-digital converter module (see Section 11.). PTD6 and PTD7 each has high current drive (25mA sink) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED driving (sink) capability.
NOTE:
PTD0-PTD1 are available on MC68H(R)C908JL3E only.
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12.5.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins.
Address: $0003 Bit 7 Read: PTD7 Write: Reset: Additional Functions LED (Sink) LED (Sink) Unaffected by reset LED (Sink) ADC8 TCH1
25mA sink 25mA sink
(Slow Edge) (Slow Edge)
6 PTD6
5 PTD5
4 PTD4
3 PTD3
2 PTD2
1 PTD1
Bit 0 PTD0
LED (Sink) ADC9 ADC10 ADC11
TCH0
5k pull-up 5k pull-up
Figure 12-9. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. ADC[11:8] -- ADC channels 11 to 8 ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Section 11. Analog-to-Digital Converter (ADC). TCH[1:0] -- Timer Channel I/O The TCH1 and TCH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD4/TCH0 and PTD5/TCH1 pins are timer channel I/O pins or general-purpose I/O pins. See Section 10. Timer Interface Module (TIM).
Technical Data 162 Input/Output (I/O) Ports MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Input/Output (I/O) Ports Port D
12.5.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer.
Address: $0007 Bit 7 Read: DDRD7 Write: Reset: 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 6 5 4 3 2 1 Bit 0
Figure 12-10. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 12-11 shows the port D I/O logic.
READ DDRD ($0007) PTDPU[6:7] WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx 5k
READ PTD ($0003)
PTD[0:3] To Analog-To-Digital Converter PTD[4:5] To Timer
Figure 12-11. Port D I/O Circuit
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Input/Output (I/O) Ports
When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port D pins. Table 12-4. Port D Pin Functions
DDRD Bit 0 1 PTD Bit X
(1)
I/O Pin Mode Input, Hi-Z Output
(2)
Accesses to DDRD Read/Write DDRD[7:0] DDRD[7:0]
Accesses to PTD Read Pin Pin Write PTD[7:0](3) PTD[7:0]
X
Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
12.5.3 Port D Control Register (PDCR) The port D control register enables/disables the pull-up resistor and slow-edge high current capability of pins PTD6 and PTD7.
Address: $000A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 3 2 1 Bit 0
Figure 12-12. Port D Control Register (PDCR) SLOWDx -- Slow Edge Enable The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink) of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx. 1 = Slow edge enabled; pin is open-drain output 0 = Slow edge disabled; pin is push-pull PTDPUx -- Pull-up Enable The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and PTD7 respectively, regardless the status of DDRDx bit. 1 = Enable 5k pull-up 0 = Disable 5k pull-up
Technical Data 164 Input/Output (I/O) Ports MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 13. External Interrupt (IRQ)
13.1 Contents
13.2 13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.5 13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .169 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 169
13.2 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
13.3 Features
Features of the IRQ module include the following: * * * * * * A dedicated external interrupt pin, IRQ1 IRQ1 interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Selectable internal pullup resistor
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA External Interrupt (IRQ)
Technical Data 165
External Interrupt (IRQ) 13.4 Functional Description
A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 13-1 shows the structure of the IRQ module. Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs: * * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic one to the ACK1 bit clears the IRQ1 latch. Reset -- A reset automatically clears the interrupt latch.
*
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or falling-edge and low-leveltriggered. The MODE1 bit in the INTSCR controls the triggering sensitivity of the IRQ1 pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK1 bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK1 bit is clear.
Technical Data 166 External Interrupt (IRQ)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
External Interrupt (IRQ) Functional Description
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests.(See 7.6 Exception Control.)
ACK1 RESET INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD IRQPUD
INTERNAL
PULLUP DEVICE
TO CPU FOR BIL/BIH INSTRUCTIONS
VDD D CLR Q SYNCHRONIZER
IRQF1
IRQ1
CK IRQ1 FF IMASK1
IRQ1 INTERRUPT REQUEST
MODE1 HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 13-1. IRQ Module Block Diagram
Addr. Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Bit 7 0 6 0 5 0 4 0 3 IRQF1 2 0 ACK1 0 0 0 0 0 0 1 IMASK1 0 Bit 0 MODE1 0
$001D
= Unimplemented
Figure 13-2. IRQ I/O Register Summary 13.4.1 IRQ1 Pin A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch. If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive. With MODE1 set, both of the following actions must occur to clear IRQ1:
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA External Interrupt (IRQ) Technical Data 167
External Interrupt (IRQ)
* Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the interrupt status and control register (INTSCR). The ACK1 bit is useful in applications that poll the IRQ1 pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ1 pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ1 pin to logic one -- As long as the IRQ1 pin is at logic zero, IRQ1 remains active.
*
The vector fetch or software clear and the return of the IRQ1 pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ1 pin is at logic zero. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch. The IRQF1 bit in the INTSCR register can be used to check for pending interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE: NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pull-up resistor to VDD is connected to the IRQ1 pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
Technical Data 168 External Interrupt (IRQ)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
External Interrupt (IRQ) IRQ Module During Break Interrupts
13.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 7. System Integration Module (SIM).) To allow software to clear the IRQ1 latch during a break interrupt, write a logic one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
13.6 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: * * * *
Address:
Shows the state of the IRQ1 flag Clears the IRQ1 latch Masks IRQ1 and interrupt request Controls triggering sensitivity of the IRQ1 interrupt pin
$001D Bit 7 6 0 5 0 4 0 3 IRQF1 IMASK1 MODE1 0 ACK1 0 0 0 0 0 0 0 2 1 Bit 0
Read: Write: Reset:
0
= Unimplemented
Figure 13-3. IRQ Status and Control Register (INTSCR)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA External Interrupt (IRQ)
Technical Data 169
External Interrupt (IRQ)
IRQF1 -- IRQ1 Flag This read-only status bit is high when the IRQ1 interrupt is pending. 1 = IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 -- IRQ1 Interrupt Request Acknowledge Bit Writing a logic one to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic zero. Reset clears ACK1. IMASK1 -- IRQ1 Interrupt Mask Bit Writing a logic one to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1. 1 = IRQ1 interrupt requests disabled 0 = IRQ1 interrupt requests enabled MODE1 -- IRQ1 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only
Address: $001E Bit 7 Read: IRQPUD Write: Reset: POR: 0 0 R 0 0 = Reserved 0 0
Not affected Not affected
6 R
5 R
4 LVIT1
3 LVIT0
2 R 0 0
1 R 0 0
Bit 0 R 0 0
0
0
Figure 13-4. Configuration Register 2 (CONFIG2) IRQPUD -- IRQ1 Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ1 pin and VDD
Technical Data 170 External Interrupt (IRQ)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents
14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 175 14.4.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 176 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.6 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .177
14.2 Introduction
The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which are accessible via PTA0-PTA6 pins.
14.3 Features
Features of the keyboard interrupt module include the following: * * * * Seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Software configurable pull-up device if input pin is configured as input port bit Programmable edge-only or edge- and level- interrupt sensitivity Exit from low-power modes
Technical Data 171
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Keyboard Interrupt Module (KBI)
Addr.
Register Name Read: Keyboard Status and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset:
Bit 7 0
6 0
5 0
4 0
3 KEYF
2 0
1 IMASKK
Bit 0 MODEK 0 KBIE0 0
$001A
ACKK 0 0 KBIE6 0 0 KBIE5 0 KBIE4 0 KBIE3 0 KBIE2 0 KBIE1 0 0 0 0 0 0 0
$001B
= Unimplemented
Figure 14-1. KBI I/O Register Summary
14.4 Functional Description
INTERNAL BUS
KBI0 VDD . KBIE0 TO PULLUP ENABLE . KBI6 . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request
CK
KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE6 TO PULLUP ENABLE
Figure 14-2. Keyboard Interrupt Block Diagram Writing to the KBIE6-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pull-up device irrespective of PTAPUEx bits in the port A input pull-up enable register (see 12.3.3 Port A Input Pull-up Enable Register (PTAPUE)). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request.
Technical Data 172 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Keyboard Interrupt Module (KBI) MOTOROLA
Keyboard Interrupt Module (KBI) Functional Description
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low.
*
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 173
Keyboard Interrupt Module (KBI)
If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, disable the pullup device, use the data direction register to configure the pin as an input and then read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
14.4.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and
Technical Data 174 MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Keyboard Interrupt Module (KBI) MOTOROLA
Keyboard Interrupt Module (KBI) Functional Description
level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
14.4.2 Keyboard Status and Control Register * * * *
Address:
Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
$001A Bit 7 6 0 5 0 4 0 3 KEYF 2 0 IMASKK MODEK 0 ACKK 0 0 0 0 0 0 0 1 Bit 0
Read: Write: Reset:
0
= Unimplemented
Figure 14-3. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as logic 0's. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on portA. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI) Technical Data 175
Keyboard Interrupt Module (KBI)
ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK-- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-A. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-A. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
14.4.3 Keyboard Interrupt Enable Register The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin.
Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 6 5 4 3 2 1 Bit 0
Figure 14-4. Keyboard Interrupt Enable Register (KBIER) KBIE6-KBIE0 -- Port-A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin
Technical Data 176
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Keyboard Interrupt Module (KBI) MOTOROLA
Keyboard Interrupt Module (KBI) Low-Power Modes
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
14.5.1 Wait Mode The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
14.5.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
14.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 177
Keyboard Interrupt Module (KBI)
Technical Data 178
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Keyboard Interrupt Module (KBI) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 15. Computer Operating Properly (COP)
15.1 Contents
15.2 15.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5 15.6 15.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .184
15.2 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP)
Technical Data 179
Computer Operating Properly (COP) 15.3 Functional Description
Figure 15-1 shows the structure of the COP module.
SIM 2OSCOUT 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR ALL STAGES
CLEAR STAGES 5-12
INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) NOTE: 1. See SIM section for more details. CLEAR COP COUNTER
Figure 15-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 218 - 24 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
Technical Data 180
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Computer Operating Properly (COP) MOTOROLA
COP TIMEOUT
Computer Operating Properly (COP) I/O Signals
NOTE:
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 x 2OSCOUT cycles and sets the COP bit in the reset status register (RSR). (See 7.8.2 Reset Status Register (RSR).).
NOTE:
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
15.4 I/O Signals
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 2OSCOUT 2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal to the crystal frequency or the RC-oscillator frequency.
15.4.2 COPCTL Write Writing any value to the COP control register (COPCTL) (see 15.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.
15.4.3 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 x 2OSCOUT cycles after power-up.
15.4.4 Internal Reset An internal reset clears the SIM counter and the COP counter.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP) Technical Data 181
Computer Operating Properly (COP)
15.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter.
15.4.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). (See Section 5. Configuration Register (CONFIG).)
15.4.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Address: $001F Bit 7 Read: COPRS Write: Reset: 0 R 0 = Reserved 0 0 0 0 0 0 R R LVID R SSREC STOP COPD 6 5 4 3 2 1 Bit 0
Figure 15-2. Configuration Register 1 (CONFIG1) COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (213 - 24) x 2OSCOUT cycles 0 = COP timeout period is (218 - 24) x 2OSCOUT cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
Technical Data 182
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Computer Operating Properly (COP) MOTOROLA
Computer Operating Properly (COP) COP Control Register
15.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when VDD + VHI is present on the IRQ1 pin or on the RST pin.
15.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
15.8.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP)
Technical Data 183
Computer Operating Properly (COP)
15.8.2 Stop Mode Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
15.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin.
Technical Data 184
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Computer Operating Properly (COP) MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents
16.2 16.3 16.4 16.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 186
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
16.3 Features
Features of the LVI module include the following: * * Selectable LVI trip voltage Selectable LVI circuit disable
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Low Voltage Inhibit (LVI)
Technical Data 185
Low Voltage Inhibit (LVI) 16.4 Functional Description
Figure 16-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which VDD level the LVI module should take actions. The LVI module generates one output signal: LVI Reset -- an reset signal will be generated to reset the CPU when VDD drops to below the set trip point.
VDD
LVID
VDD > LVITRIP = 0 LOW VDD DETECTOR VDD < LVITRIP = 1
LVI RESET
LVIT1
LVIT0
Figure 16-1. LVI Module Block Diagram
16.5 LVI Control Register (CONFIG2/CONFIG1)
Address: $001E Bit 7 Read: IRQPUD Write: Reset: POR: 0 0 R 0 0 = Reserved 0 0
Not affected Not affected
6 R
5 R
4 LVIT1
3 LVIT0
2 R 0 0
1 R 0 0
Bit 0 R 0 0
0
0
Figure 16-2. Configuration Register 2 (CONFIG2)
Technical Data 186 Low Voltage Inhibit (LVI) MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Low Voltage Inhibit (LVI) Low-Power Modes
Address:
$001F Bit 7 6 R 0 = Reserved 5 R 0 4 LVID 0 3 R 0 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Read: COPRS Write: Reset: 0 R
Figure 16-3. Configuration Register 1 (CONFIG1) LVID -- Low Voltage Inhibit Disable Bit 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled LVIT1, LVIT0 -- LVI Trip Voltage Selection These two bits determine at which level of VDD the LVI module will come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset only.
LVIT1 0 0 1 1 LVIT0 0 1 0 1 Trip Voltage(1) VLVR3 (2.4V) VLVR3 (2.4V) VLVR5 (4.0V) Reserved Comments For VDD =3V operation For VDD =3V operation For VDD =5V operation
1. See Section 18. Electrical Specifications for full parameters.
16.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-powerconsumption standby modes. 16.6.1 Wait Mode The LVI module, when enabled, will continue to operate in WAIT Mode. 16.6.2 Stop Mode The LVI module, when enabled, will continue to operate in STOP Mode.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Low Voltage Inhibit (LVI) Technical Data 187
Low Voltage Inhibit (LVI)
Technical Data 188 Low Voltage Inhibit (LVI)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 17. Break Module (BREAK)
17.1 Contents
17.2 17.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .192 17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 193 17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .194 17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 196 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
17.2 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Break Module (BREAK)
Technical Data 189
Break Module (BREAK) 17.3 Features
Features of the break module include the following: * * * * Accessible I/O registers during the break Interrupt CPU-generated break interrupts Software-generated break interrupts COP disabling during break interrupts
17.4 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic one to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 17-1 shows the structure of the break module.
Technical Data 190 Break Module (BREAK)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Break Module (BREAK) Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
IAB[7:0]
Figure 17-1. Break Module Block Diagram
Addr.
Register Name Read: Break Status Register Write: (BSR) Reset: Read: Break Flag Control Register Write: (BFCR) Reset: Read: Break Address High Register Write: (BRKH) Reset: Read: Break Address low Register Write: (BRKL) Reset:
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW See note 0
Bit 0 R
$FE00
$FE03
BCFE 0 Bit15 0 Bit7 0 BRKE 0
R
R
R
R
R
R
R
$FE0C
Bit14 0 Bit6 0 BRKA 0
Bit13 0 Bit5 0 0
Bit12 0 Bit4 0 0
Bit11 0 Bit3 0 0
Bit10 0 Bit2 0 0
Bit9 0 Bit1 0 0
Bit8 0 Bit0 0 0
$FE0D
Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset:
Note: Writing a logic 0 clears SBSW.
0
0 R
0 = Reserved
0
0
0
= Unimplemented
Figure 17-2. Break I/O Register Summary
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Break Module (BREAK)
Technical Data 191
Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR) and see the Break Interrupts subsection for each module.) 17.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 17.4.3 TIM During Break Interrupts A break interrupt stops the timer counter. 17.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin.
17.5 Break Module Registers
These registers control and monitor operation of the break module: * * * * *
Technical Data 192 Break Module (BREAK)
Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) Break status register (BSR) Break flag control register (BFCR)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Break Module (BREAK) Break Module Registers
17.5.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits.
Address: $FE0E Bit 7 Read: BRKE Write: Reset: 0 0 0 0 0 0 0 0 BRKA 6 5 0 4 0 3 0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 17-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Break Module (BREAK)
Technical Data 193
Break Module (BREAK)
17.5.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Figure 17-4. Break Address Register High (BRKH)
Address: $FE0D Bit 7 Read: Bit 7 Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 17-5. Break Address Register Low (BRKL)
17.5.3 Break Status Register The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address: $FE00 Bit 7 Read: R Write: Reset: R = Reserved R R R R R 6 5 4 3 2 1 SBSW Note(1) 0 1. Writing a logic zero clears SBSW. R Bit 0
Figure 17-6. Break Status Register (BSR)
Technical Data 194 Break Module (BREAK)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Break Module (BREAK) Break Module Registers
SBSW -- SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,BSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited ; by break. ; If RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Break Module (BREAK)
Technical Data 195
Break Module (BREAK)
17.5.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Bit 7 Read: BCFE Write: Reset: 0 R = Reserved R R R R R R R $FE03 6 5 4 3 2 1 Bit 0
Figure 17-7. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 17.6.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see 7.7 Low-Power Modes). Clear the SBSW bit by writing logic zero to it. 17.6.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 7.8 SIM Registers.
Technical Data 196 Break Module (BREAK) MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 18. Electrical Specifications
18.1 Contents
18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 199 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 200 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 202 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 203
18.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
18.2 Introduction
This section contains electrical and timing specifications.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 197
Electrical Specifications 18.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to Sections 18.6 and 18.9 for guaranteed operating conditions. Table 18-1. Absolute Maximum Ratings
Characteristic(1) Supply voltage Input voltage Mode entry voltage, IRQ1 pin Maximum current per pin excluding VDD and VSS Storage temperature Maximum current out of VSS Maximum current into VDD
NOTES: 1. Voltages referenced to VSS.
Symbol VDD VIN
VDD +VHI
Value -0.3 to +6.0 VSS -0.3 to VDD +0.3 VSS -0.3 to +8.5
Unit V V V mA
I TSTG IMVSS IMVDD
25
-55 to +150 100 100
C
mA mA
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
Technical Data 198 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications Functional Operating Range
18.4 Functional Operating Range
Table 18-2. Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value - 40 to +125 5 10% - 40 to +85 3 10% Unit
C
V
18.5 Thermal Characteristics
Table 18-3. Thermal Characteristics
Characteristic Thermal resistance 20-pin PDIP 20-pin SOIC 28-pin PDIP 28-pin SOIC 48-pin LQFP I/O pin power dissipation Power dissipation(1) Symbol Value 70 70 70 70 80 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) Unit
JA
C/W C/W C/W C/W C/W
W W
PI/O PD
Constant(2) Average junction temperature
K TJ
W/C
C
NOTES: 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 199
Electrical Specifications 18.6 5V DC Electrical Characteristics
Table 18-4. DC Electrical Characteristics (5V)
Characteristic(1) Output high voltage (ILOAD = -2.0mA) PTA0-PTA6, PTB0-PTB7, PTD0-PTD7 Output low voltage (ILOAD = 1.6mA) PTA6, PTB0-PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 25mA) PTD6, PTD7 LED drives (VOL = 3V) PTA0-PTA5, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 Input low voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 VDD supply current, fOP = 4MHz Run(3) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Wait(4) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Stop(5) (-40C to 85C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E (-40C to 125C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Monitor mode entry voltage Technical Data 200 Electrical Specifications Symbol VOH VOL VOL IOL Min VDD -0.8 -- -- 10 Typ(2) -- -- -- 16 Max -- 0.4 0.5 22 Unit V V V mA
VIH
0.7 x VDD
--
VDD
V
VIL
VSS
--
0.3 x VDD
V
-- -- -- --
10 4.5 6 1
11 5 6.5 1.5
mA mA mA mA
IDD
-- -- -- -- IIL IIN COUT CIN VPOR RPOR VDD +VHI -- -- -- -- 0 0.035 1.5 x VDD
2 2 2 2 -- -- -- -- -- -- --
5 5 10 10
A A A A A A
pF mV V/ms V
10 1
12 8 100 -- 8.5
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications 5V Control Timing
Table 18-4. DC Electrical Characteristics (5V)
Characteristic(1) Pullup resistors(8) PTD6, PTD7 RST, IRQ1, PTA0-PTA6 LVI reset voltage Symbol RPU1 RPU2 VLVR5 Min Typ(2) 3.3 26 4.0 Max Unit
1.8 16 3.6
4.8 36 4.4
k k V
NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V.
18.7 5V Control Timing
Table 18-5. Control Timing (5V)
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 750 Max 8 -- Unit MHz ns
NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 201
Electrical Specifications 18.8 5V Oscillator Characteristics
Table 18-6. Oscillator Component Specifications (5V)
Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance(2) Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) RC oscillator external R RC oscillator external C Symbol fOSCXCLK fRCCLK fOSCXCLK CL C1 C2 RB RS REXT CEXT -- Min -- 2 dc -- -- -- -- -- Typ 10 10 -- -- 2 x CL 2 x CL 10 M -- See Figure 18-1 10 -- pF Max 32 12 32 -- -- -- -- -- Unit MHz MHz MHz
NOTES: 1. No more than 10% duty cycle deviation from 50%. 2. Consult crystal vendor data sheet. 3. Not required for high frequency crystals.
14 RC frequency, fRCCLK (MHz) 12 10 8 6 VDD 4 2 0 0 10 20 30 Resistor, REXT (k) 40 50 REXT CEXT CEXT = 10 pF 5V @ 25C OSC1
MCU
Figure 18-1. RC vs. Frequency (5V @25C)
Technical Data 202 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications 3V DC Electrical Characteristics
18.9 3V DC Electrical Characteristics
Table 18-7. DC Electrical Characteristics (3V)
Characteristic(1) Output high voltage (ILOAD = -1.0mA) PTA0-PTA6, PTB0-PTB7, PTD0-PTD7 Output low voltage (ILOAD = 0.8mA) PTA6, PTB0-PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 20mA) PTD6, PTD7 LED drives (VOL = 1.8V) PTA0-PTA5, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 Input low voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 VDD supply current, fOP = 2MHz Run(3) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Wait(4) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Stop(5) (-40C to 85C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Monitor mode entry voltage Symbol VOH VOL VOL IOL Min VDD - 0.4 -- -- 3 Typ(2) -- -- -- 6 Max -- 0.4 0.5 10 Unit V V V mA
VIH
0.7 x VDD
--
VDD
V
VIL
VSS
--
0.3 x VDD
V
-- -- IDD -- --
3 1.5 1.5 0.2
3.5 2 2 0.3
mA mA mA mA
-- -- IIL IIN COUT CIN VPOR RPOR VDD +VHI -- -- -- -- 0 0.035 1.5 x VDD
1 1 -- -- -- -- -- -- --
5 5
A A A A
pF mV V/ms V
10 1
12 8 100 -- 8.5
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 203
Electrical Specifications
Table 18-7. DC Electrical Characteristics (3V)
Characteristic(1) Pullup resistors(8) PTD6, PTD7 RST, IRQ1, PTA0-PTA6 LVI reset voltage Symbol RPU1 RPU2 VLVR3 Min Typ(2) 3.3 26 2.4 Max Unit
1.8 16 2.0
4.8 36 2.69
k k V
NOTES: 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V.
18.10 3V Control Timing
Table 18-8. Control Timing (3V)
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 1.5 Max 4 -- Unit MHz
s
NOTES: 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Technical Data 204 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications 3V Oscillator Characteristics
18.11 3V Oscillator Characteristics
Table 18-9. Oscillator Component Specifications (3V)
Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance(2) Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) RC oscillator external R RC oscillator external C Symbol fOSCXCLK fRCCLK fOSCXCLK CL C1 C2 RB RS REXT CEXT -- Min -- 2 dc -- -- -- -- -- Typ 8 8 -- -- 2 x CL 2 x CL 10 M -- See Figure 18-2 10 -- pF Max 16 12 16 -- -- -- -- -- Unit MHz MHz MHz
NOTES: 1. No more than 10% duty cycle deviation from 50%. 2. Consult crystal vendor data sheet. 3. Not required for high frequency crystals.
14 RC frequency, fRCCLK (MHz) 12 10 8 6 VDD 4 2 0 0 10 20 30 Resistor, REXT (k) 40 50 REXT CEXT CEXT = 10 pF 3V @ 25C OSC1
MCU
Figure 18-2. RC vs. Frequency (3V @25C)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 205
Electrical Specifications 18.12 Typical Supply Currents
14 12 10 IDD (mA) 8 6 4 2 MC68HC908JL3E/JK3E/JK1E 5.5 V 3.3 V 0 1 2 3 4 5 6 fOP or fBUS (MHz) 7 8 9
0
Figure 18-3. Typical Operating IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned On (25 C)
10 8 IDD (mA) 6 4 2 0 0 1 2 3 4 5 6 fOP or fBUS (MHz) 7 8 9 MC68HRC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 18-4. Typical Operating IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned On (25 C)
Technical Data 206 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications Typical Supply Currents
10 8 IDD (mA) 6 4 2 0 0 1 2 3 4 5 6 fOP or fBUS (MHz) 7 8 9 MC68HC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 18-5. Typical Wait Mode IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 C)
2 1.75 1.50 IDD (mA) 1.25 1 0.75 0.5 0.25 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 MC68HRC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 18-6. Typical Wait Mode IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 C)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 207
Electrical Specifications 18.13 ADC Characteristics
Table 18-10. ADC Characteristics
Characteristic Supply voltage Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(1) Zero input reading(2) Full-scale reading(3) Input capacitance Input leakage(3) Port B/port D Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI -- Min 2.7 (VDD min) VSS 8 Max 5.5 (VDD max) VDD 8 Unit V V Bits LSB MHz V tAIC cycles 15 -- 01 FF (20) 8 tAIC cycles tAIC cycles Hex Hex pF VIN = VSS VIN = VDD Not tested Includes quantization tAIC = 1/fADIC, tested only at 1 MHz Comments
0.5
0.5 VSS 16 14 5 00 FE -- --
1.5
1.048 VDD
1
A
NOTES: 1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
Technical Data 208 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Electrical Specifications Memory Characteristics
18.14 Memory Characteristics
Table 18-11. Memory Characteristics
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time FLASH mass erase time FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program hv period FLASH row erase endurance(6) FLASH row program endurance FLASH data retention time(8)
(7)
Symbol VRDR -- fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvh1 tpgs tPROG trcv(4) tHV(5) -- -- --
Min 1.3 1 32k 1 4 10 5 100 5 30 1 -- 10k 10k 10
Max -- -- 8M -- -- -- -- -- -- 40 -- 4 -- -- --
Unit V MHz Hz ms ms
s s s s s s
ms cycles cycles years
NOTES: 1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG x 32) tHV max. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 209
Electrical Specifications
Technical Data 210 Electrical Specifications
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 19. Mechanical Specifications
19.1 Contents
19.2 19.3 19.4 19.5 19.6 19.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.2 Introduction
This section gives the dimensions for: * * * * * 20-pin plastic dual in-line package (case #738) 20-pin small outline integrated circuit package (case #751D) 28-pin plastic dual in-line package (case #710) 28-pin small outline integrated circuit package (case #751F) 48-pin low-profile quad flat pack (case #932)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Mechanical Specifications
Technical Data 211
Mechanical Specifications 19.3 20-Pin PDIP
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
Figure 19-1. 20-Pin PDIP (Case #738)
19.4 20-Pin SOIC
-A-
20 11
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
Figure 19-2. 20-Pin SOIC (Case #751D)
Technical Data 212
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Mechanical Specifications MOTOROLA
Mechanical Specifications 28-Pin PDIP
19.5 28-Pin PDIP
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
28
15
B
1 14
A N
C
L
H
G
F D
K
SEATING PLANE
M
J
Figure 19-3. 28-Pin PDIP (Case #710)
19.6 28-Pin SOIC
-A28 15 14X
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B1 14
P 0.010 (0.25)
M
B
M
28X
D
M
0.010 (0.25)
TA
S
B
S
M R C
X 45 DIM A B C D F G J K M P R
26X
G K
-TSEATING PLANE
F J
MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.01 10.55 0.25 0.75
INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
Figure 19-4. 28-Pin SOIC (Case #751F)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Mechanical Specifications
Technical Data 213
Mechanical Specifications 19.7 48-Pin LQFP
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1 5 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M
TOP & BOTTOM
R
GAUGE PLANE
C F D 0.080
M
E
AC T-U Z H DETAIL AD AA W L K
SECTION AE-AE
Figure 19-5. 48-Pin LQFP (Case #932)
Technical Data 214
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 Mechanical Specifications MOTOROLA
0.250
N
J
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Section 20. Ordering Information
20.1 Contents
20.2 20.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
20.2 Introduction
This section contains ordering numbers for the MC68H(R)C908JL3E, MC68H(R)C908JK3E, and MC68H(R)C908JK1E.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA Ordering Information
Technical Data 215
Ordering Information 20.3 MC Order Numbers
Table 20-1. MC Order Numbers
MC order number
MC68HC908JL3ECFA MC68HC908JL3EMFA MC68HRC98JL3ECFA MC68HRC98JL3EMFA MC68HC908JL3ECP MC68HC908JL3EMP MC68HC908JL3ECDW MC68HC908JL3EMDW MC68HRC98JL3ECP MC68HRC98JL3EMP MC68HRC98JL3ECDW MC68HRC98JL3EMDW MC68HC908JK3ECP MC68HC908JK3EMP MC68HC908JK3ECDW MC68HC908JK3EMDW MC68HRC98JK3ECP MC68HRC98JK3EMP MC68HRC98JK3ECDW MC68HRC98JK3EMDW MC68HC908JK1ECP MC68HC908JK1EMP MC68HC908JK1ECDW MC68HC908JK1EMDW MC68HRC98JK1ECP MC68HRC98JK1EMP MC68HRC98JK1ECDW MC68HRC98JK1EMDW
Oscillator type
Crystal oscillator
FLASH memory
Package
4096 Bytes RC oscillator
48-pin LQFP
Crystal oscillator 4096 Bytes RC oscillator 28-pin package
Crystal oscillator 4096 Bytes RC oscillator 20-pin package Crystal oscillator 1536 Bytes RC oscillator
Notes: C = -40 C to +85 C M = -40 C to +125 C (available for VDD = 5V only) P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) FA = Low-Profile Quad Flat Pack (LQFP)
Technical Data 216 Ordering Information
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA
Technical Data - MC68H(R)C908JL3E/JK3E/JK1E
Appendix A. MC68HLC908JL3E/JK3E/JK1E
A.1 Contents
A.2 A.3 A.4 A.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Oscillator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
A.6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 A.6.1 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . 218 A.6.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 219 A.6.3 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 A.6.4 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .220 A.6.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 A.6.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 A.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
A.2 Introduction
This appendix introduces three devices, that are low-voltage versions of MC68HC908JL3E/JK3E/JK1E: * * * MC68HLC908JL3E MC68HLC908JK3E MC68HLC908JK1E
The entire data book apply to these low-voltage devices, with exceptions outlined in this appendix.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA MC68HLC908JL3E/JK3E/JK1E
Technical Data 217
MC68HLC908JL3E/JK3E/JK1E A.3 FLASH Memory
The FLASH memory can be read at minimum VDD of 2.2V. Program or erase operations require a minimum VDD of 2.7V.
A.4 Low-Voltage Inhibit
There is no low-voltage inhibit circuit. Therefore, no low-voltage reset. The associated register bits are reserved bits.
A.5 Oscillator Options
Only crystal oscillator or direct clock input is supported.
A.6 Electrical Specifications
Electrical specifications for low-voltage devices are given in the following tables.
A.6.1 Functional Operating Range Table A-1. Operating Range
Characteristic Operating temperature range Operating voltage range Operating voltage for FLASH memory program and erase operations Symbol TA VDD VDD Value 0 to +85 2.2 to 5.5 2.7 to 5.5 Unit
C
V V
Technical Data 218
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MC68HLC908JL3E/JK3E/JK1E MOTOROLA
MC68HLC908JL3E/JK3E/JK1E
A.6.2 DC Electrical Characteristics Table A-2. DC Electrical Characteristics
Characteristic(1) Output high voltage (ILOAD = -1.0mA) PTA0-PTA6, PTB0-PTB7, PTD0-PTD7 Output low voltage (ILOAD = 0.8mA) PTA6, PTB0-PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 15mA) PTD6, PTD7 Input high voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 Input low voltage PTA0-PTA6, PTB0-PTB7, PTD0-PTD7, RST, IRQ1, OSC1 VDD supply current (VDD = 2.4V, fOP = 2MHz) Run(3) Wait(4) Stop(5) 0C to 85C Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Pullup resistors(8) PTD6, PTD7 RST, IRQ1, PTA0-PTA6 Symbol VOH VOL VOL VIH Min VDD - 0.4 -- -- 0.7 x VDD Typ(2) -- -- -- Max -- 0.4 0.5 Unit V V V
--
VDD
V
VIL
VSS
--
0.2 x VDD
V
IDD
-- -- -- -- -- -- -- 0 0.02 1.8 16
2 1 1 -- -- -- -- -- -- 3.3 26
3.5 1.5 3
mA mA A
IIL IIN COUT CIN VPOR RPOR RPU1 RPU2
10 1
12 8 100 -- 4.8 36
A A
pF mV V/ms k k
NOTES: 1. VDD = 2.4 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA MC68HLC908JL3E/JK3E/JK1E
Technical Data 219
MC68HLC908JL3E/JK3E/JK1E
A.6.3 Control Timing Table A-3. Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 1.5 Max 2 -- Unit MHz
s
NOTES: 1. VDD = 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
A.6.4 Oscillator Characteristics Table A-4. Oscillator Component Specifications
Characteristic Crystal frequency, XTALCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance(2) Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) Symbol fOSCXCLK fOSCXCLK CL C1 C2 RB RS Min -- dc -- -- -- -- -- Typ -- -- -- 2 x CL 2 x CL 10 M -- Max 8 8 -- -- -- -- -- Unit MHz MHz
NOTES: 1. No more than 10% duty cycle deviation from 50% 2. Consult crystal vendor data sheet 3. Not Required for high frequency crystals
Technical Data 220
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MC68HLC908JL3E/JK3E/JK1E MOTOROLA
MC68HLC908JL3E/JK3E/JK1E
A.6.5 ADC Characteristics Table A-5. ADC Characteristics
Characteristic Supply voltage Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(1) Zero input reading(2) Full-scale reading(3) Input capacitance Input leakage(3) Port B/port D Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI -- Min 2.2 (VDD min) VSS 8 Max 5.5 (VDD max) VDD 8 Unit V V Bits LSB MHz V tAIC cycles tAIC cycles tAIC cycles Hex Hex pF VIN = VSS VIN = VDD Not tested Includes quantization tAIC = 1/fADIC, tested only at 1 MHz Comments
0.5
0.5 VSS 14 14 5 00 FE -- --
2
1.048 VDD -- 15 -- 01 FF (20) 8
1
A
NOTES: 1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA MC68HLC908JL3E/JK3E/JK1E
Technical Data 221
MC68HLC908JL3E/JK3E/JK1E
A.6.6 Memory Characteristics The FLASH memory can only be read at an operating voltage of 2.2 to 5.5V. Program and erase are achieved at an operating voltage of 2.7 to 5.5V. The program and erase parameters in Table A-6 are for VDD = 2.7 to 5.5V only. Table A-6. Memory Characteristics
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time FLASH mass erase time FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program hv period FLASH row erase endurance(6) FLASH row program endurance(7) FLASH data retention time
(8)
Symbol VRDR -- fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvhl tpgs tPROG trcv(4) tHV(5) -- -- --
Min 1.3 1 32k 1 4 10 5 100 5 30 1 -- 10k 10k 10
Max -- -- 8M -- -- -- -- -- -- 40 -- 4 -- -- --
Unit V MHz Hz ms ms
s s s s s s
ms cycles cycles years
NOTES: 1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG x 32) tHV max. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
Technical Data 222
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MC68HLC908JL3E/JK3E/JK1E MOTOROLA
MC68HLC908JL3E/JK3E/JK1E
A.7 MC Order Numbers
Table A-7 shows the ordering numbers for the low-voltage devices. Table A-7. MC68HLC908JL3E/JK3E/JK1E Order Numbers
MC order number
MC68HLC98JL3EIFA MC68HLC98JL3EIP MC68HLC98JL3EIDW MC68HLC98JK3EIP MC68HLC98JK3EIDW MC68HLC98JK1EIP MC68HLC98JK1EIDW
Oscillator type
Crystal oscillator Crystal oscillator Crystal oscillator Crystal oscillator
FLASH memory
4096 Bytes 4096 Bytes 4096 Bytes
Package
48-pin LQFP 28-pin package
20-pin package 1536 Bytes
Notes: I = 0 C to +85 C P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) FA = Low-Profile Quad Flat Pack (LQFP)
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MOTOROLA MC68HLC908JL3E/JK3E/JK1E
Technical Data 223
MC68HLC908JL3E/JK3E/JK1E
Technical Data 224
MC68H(R)C908JL3E/JK3E/JK1E -- Rev. 2.0 MC68HLC908JL3E/JK3E/JK1E MOTOROLA
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MC68HC908JL3E/D Rev. 2.0 12/2002

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